Datasheet

DTM65523C
4 GB, 240-Pin DDR2 FB-DIMM
Document 06026, Revision A, 29-Sep-10, Dataram Corporation © 2010 Page 15
Bit 5, Bit 4. TBD 0
Bit 6. High Temperature Self-Refresh - 1-Required
Bit 7. Double Refresh Requirement -
1-
Supported
Tcasemax Delta
Bit 3 ~ Bit 0. DT4R4W Delta, Subfield B: 0.4 °C - 0.4
33
Bit 7 ~ Bit 4. Tcasemax, Subfield A: 2 °C - 10
51
34 Thermal Resistance of SDRAM Package °C/W 58 74
SDRAM Case Temperature Rise from Ambient due to Activate-Precharge minus 2.8 °C
offset temperature (DT0) °C
Bit 1, Bit 0. Reserved 0
35
Bit 7 ~ Bit 2. DT0 - 6.3
54
36
SDRAM Case Temperature Rise from Ambient due to Precharge/Quiet
Standby (DT2N/DT2Q) °C
5.7 39
37
SDRAM Case Temperature Rise from Ambient due to Precharge Power-
Down (DT2P) °C
1.44 60
38
SDRAM Case Temperature Rise from Ambient due to Active Standby (DT3N)
°C
6.9 2E
SDRAM Case Temperature Rise from Ambient due to Page Open Burst
Read/DT4R4W Mode Bit (DT4R/DT4R4W Mode Bit)
Bit 0. DT4R4W Mode Bit, Subfield B: 0.4 °C 0
39
Bit 7 ~ Bit 1. DT4R, Subfield A: 0.4 °C - 14.8
4A
40
SDRAM Case Temperature Rise from Ambient due to Burst Refresh
(DT5B) °C
24.5 31
41
SDRAM Case Temperature Rise from Ambient due to Bank Interleave Reads
with Auto-Precharge (DT7) °C
26.5 35
42-74 Reserved UNUSED 00
75 QR Control 29
76 QR ODT control for Rank 0 and rank 1 Reads and writes 44
77 QR ODT1 and ODT2 control for reads 66
FBD ODT Definition for Rank 2 and 3
Bit 1, Bit 0. Rank 2 Data DRAM ODT - 150 Ohms
Bit 3, Bit 2. Rank 2 Ecc DRAM ODT - 150 Ohms
Bit 5, Bit 4. Rank 3 Data DRAM ODT - 150 Ohms
78
Bit 7, Bit 6. Rank 3 Ecc DRAM ODT - 150 Ohms
AA
FBD ODT Definition for Rank 0 and 1
Bit 1, Bit 0. Rank 0 Data DRAM ODT - 150 Ohms
Bit 3, Bit 2. Rank 0 Ecc DRAM ODT - Disabled
Bit 5, Bit 4. Rank 1 Data DRAM ODT - 150 Ohms
79
Bit 7, Bit 6. Rank 1 Ecc DRAM ODT - Disabled
22
80 Reserved UNUSED 00
81
Channel Protocols Supported, Least Significant Byte
02