Datasheet

DTM65523C
4 GB, 240-Pin DDR2 FB-DIMM
Document 06026, Revision A, 29-Sep-10, Dataram Corporation © 2010 Page 14
14 SDRAM Minimum CAS Latency Time (t
AA
min) 15.0ns 3C
SDRAM Write Recovery Times Supported
Bit 3 ~ Bit 0. Minimum WR (clocks) - 2
15
Bit 7 ~ Bit 4. WR Range (clocks) - 4
42
16 SDRAM Write Recovery Time (t
WR
) 15.0ns 3C
SDRAM Write Latencies Supported
Bit 3 ~ Bit 0. Minimum WL (clocks) - 3
17
Bit 7 ~ Bit 4. WL Range (clocks) - 6
63
SDRAM Additive Latencies Supported.
Bit 3 ~ Bit 0. Minimum AL (clocks)- 0
18
Bit 7 ~ Bit 4. AL Range (clocks) - 5
50
19 SDRAM Minimum RAS to CAS Delay (t
RCD
) 15.0ns 3C
20 SDRAM Minimum Row Active to Row Active Delay (t
RRD
) 7.5ns 1E
21 SDRAM Minimum Row Precharge Time (t
RP
) 15.0ns 3C
SDRAM Upper Nibbles for t
RAS
and t
RC
Bit 3 ~ Bit 0. tRAS Most Significant Nibble -
22
Bit 7 ~ Bit 4. tRC Most Significant Nibble -
00
23 SDRAM Minimum Active to Precharge Time (t
RAS
) 45.0ns B4
24 SDRAM Minimum Active to Active/Refresh Time (t
RC
) 60.0ns F0
25 SDRAM Minimum Refresh Recovery Time Delay (t
RFC
), (LSB) 127.5ns FE
26 SDRAM Minimum Refresh Recovery Time Delay (t
RFC
), (MSB) 127.5ns 01
27 SDRAM Minimum Internal Write to Read Command Delay (t
WTR
) 7.5ns 1E
28 SDRAM Minimum Internal Read to Precharge Command Delay (t
RTP
) 7.5ns 1E
SDRAM Burst Lengths Supported
Bit 0. BL = 4 - X
Bit 1. BL = 8 - X
Bit 6 ~ Bit 2.TBD
29
Bit 7. Burst Chop -
03
SDRAM Terminations Supported
Bit 0. 150 ohms ODT - X
Bit 1. 75 ohms ODT - X
Bit 2. 50 ohms ODT - X
30
Bit 6 ~ Bit 3.TBD
07
SDRAM Drivers Supported
Bit 0. Weak Driver - X
31
Bit 7 ~ Bit 1. TBD
01
SDRAM Average Refresh Interval (t
REFI
) / Double Refresh mode bit / High Temperature
self-refresh rate support indication
32
Bit 0 ~ Bit 3. Average Refresh Interval (t
REFI
) μs - 7.8
C2