Datasheet

DTM65517
8 GB - 1Gx72, 240-Pin FB-DIMM
Document 06051, Revision A, 24-Jul-08, Dataram Corporation © 2008 Page 14
SERIAL PRESENCE DETECT MATRIX
Byte# Function Value Hex
Number of SPD Bytes Written / SPD Device Size / CRC Coverage
Bit 3 ~ Bit 0. SPD Bytes Used - 176
Bit 6 ~ Bit 4. SPD Bytes Total - 256
0
Bit 7. CRC Coverage - Bytes 0-116
92
1 SPD Revision Rev. 1.1 11
2 Key Byte / DRAM Device Type
DDR2
FBDIMM
09
Voltage Levels of this Assembly
Bit 3 ~ Bit 0. Power Supply 1 - 1.5V
3
Bit 7 ~ Bit 4. Power Supply 2 - 1.8V
12
SDRAM Addressing
Bit 1, 0. Number of Banks - 8
Bit 5 ~ Bit 3.Column Address Bits - 11
4
Bit 7 ~ Bit 5. Row Address Bits - 14
49
Module Physical Attributes
Bit 3 ~ Bit 0. Module Thickness (mm) - 7<x<=8.0
Bit 4 ~ Bit 2. Module Height (mm) - 30<x<=35
5
Bit 7, 6. Reserved 0
23
Module Type
Bit 3 ~ Bit 0. Module Type - FB-DIMM
6
Bit 7 ~ Bit 4. Reserved Reserved
07
Module Organization
Bit 3 ~ Bit 0. SDRAM Device Width - 4-Bits
Bit 5 ~ Bit 3. Number of Ranks - 4 Ranks
7
Bit 7, 6. Reserved 0
20
Fine Timebase Dividend / Divisor
Bit 3 ~ Bit 0. Fine Timebase (FTB) Dividend - 0
8
Bit 7 ~ Bit 4. Fine Timebase (FTB) Divisor - 0
00
9 Medium Timebase Dividend.
1 (MTB =
0.25ns)
01
10 Medium Timebase Divisor.
4 (MTB =
0.25ns)
04
11 SDRAM Minimum Cycle Time (tCKmin). 3.0 ns 0C
12 SDRAM Maximum Cycle Time (tCKmax). 8.0 ns 20
SDRAM CAS Latencies Supported.
Bit 3 ~ Bit 0. Minimum CL (clocks) - 4
13
Bit 7 ~ Bit 4. CL Range (clocks) - 2
24
14 SDRAM Minimum CAS Latency Time (tAAmin). 15 ns 3C
SDRAM Write Recovery Times Supported
Bit 3 ~ Bit 0. Minimum WR (clocks) - 2
15
Bit 7 ~ Bit 4. WR Range (clocks) - 4
42
16 SDRAM Write Recovery Time (tWR). 15.0 ns 3C
SDRAM Write Latencies Supported
17
Bit 3 ~ Bit 0. Minimum WL (clocks) - 2
42