Datasheet

DTM64329C
4GB - 240-Pin 2Rx8 Unbuffered Non-ECC DDR3 DIMM
Document 06939, Revision A, 3-Oct-11, Dataram Corporation 

 2011 Page 8
SERIAL PRESENCE DETECT MATRIX
Byte# Function. Value Hex
Number of Bytes Used / Number of Bytes in SPD Device / CRC Coverage.
Bit 3 ~ Bit 0. SPD Bytes Used - 176
Bit 6 ~ Bit 4. SPD Bytes Total - 256
0
Bit 7. CRC Coverage - Bytes 0-
116
0x92
1
SPD Revision. Rev. 1.1
0x11
2
Key Byte / DRAM Device Type.
DDR3 SDRAM
0x0B
Key Byte / Module Type.
Bit 3 ~ Bit 0. Module Type - UDIMM
3
Bit 7 ~ Bit 4. Reserved - 0
0x02
SDRAM Density and Banks.
Bit 3 ~ Bit 0. Total SDRAM capacity, in megabits -
2GB
Bit 6 ~ Bit 4. Bank Address Bits -
8 banks
4
Bit 7. Reserved - 0
0x03
SDRAM Addressing.
Bit 2 ~ Bit 0. Column Address Bits - 10
Bit 5 ~ Bit 3. Row Address Bits - 15
5
Bit 7, 6. Reserved 0
0x19
6
Reserved. UNUSED
0x00
Module Organization.
Bit 2 ~ Bit 0. SDRAM Device Width - 8-
Bits
Bit 5 ~ Bit 3. Number of Ranks - 2-Rank
7
Bit 7, 6. Reserved 0
0x09
Module Memory Bus Width.
Bit 2 ~ Bit 0. Primary bus width, in bits - 64-
Bits
Bit 4, Bit 3. Bus width extension, in bits - 0-
Bits
8
Bit 7 ~ Bit 5. Reserved - 0
0x03
Fine Timebase (FTB) Dividend / Divisor.
Bit 3 ~ Bit 0. Fine Timebase (FTB) Divisor 2
9
Bit 7 ~ Bit 4. Fine Timebase (FTB) Dividend 5
0x52
10
Medium Timebase (MTB) Dividend. 1 (MTB =
0.125ns)
0x01
11
Medium Timebase (MTB) Divisor. 8 (MTB =
0.125ns)
0x08
12
SDRAM Minimum Cycle Time (tCKmin). 1.5ns
0x0C
13
Reserved. UNUSED
0x00
CAS Latencies Supported, Least Significant Byte.
Bit 0. CL = 4 -
Bit 1. CL = 5 -
Bit 2. CL = 6 - X
Bit 3. CL = 7 - X
Bit 4. CL = 8 - X
Bit 5. CL = 9 - X
Bit 6. CL = 10 -
14
Bit 7. CL = 11 -
0x3C