Datasheet

DTM63392F
1GB - 240-Pin Registered ECC DDR2 DIMM w/CMD/ADD Parity
Document 06010, Revision A, 27-Sep-10, Dataram Corporation © 2010 Page 6
I
DD
Specifications and Conditions (Voltages referenced to V
ss
= 0 V)
PARAMETER Symbol Test Condition
Max
Value
Unit
Operating One
Bank Active-
Precharge Current
I
DD
0
CKE is HIGH, /CS is HIGH between valid commands; Address
bus inputs are switching; Data bus inputs are switching.
770
mA
Operating One
Bank Active-Read-
Precharge Current
I
DD
1
I
OUT
= 0 mA; BL = 4, CL = 5 ns, AL = 0; CKE is HIGH, /CS is
HIGH between valid commands; Address bus inputs are
switching.
880
mA
Precharge Power-
Down Current
I
DD
2P
All banks idle; CKE is LOW; Other control and address bus inputs
are stable; Data bus inputs are floating.
250
mA
Precharge Standby
Current
I
DD
2N
All banks idle; CKE is HIGH, /CS is HIGH; Other control and
address bus inputs are switching; Data bus inputs are switching.
630
mA
Active Power-Down
Current
I
DD
3P
All banks open; CKE is LOW; Other control and address bus
inputs are stable; Data bus inputs are floating. Fast Power-down
exit (Mode Register bit 12 = 0)
330
mA
Active Standby
Current
I
DD
3N
All banks open; t
RAS
= 70 ms; CKE is HIGH, /CS is HIGH between
valid commands; Other control and address bus inputs are
switching; Data bus inputs are switching.
650
mA
Operating Burst
Write Current
I
DD
4W
Burst Write: All banks open; Continuous burst writes; BL = 4; AL =
0, CL = CL(IDD); tCK = tCK(IDD); tRAS tRAS.MAX(IDD), tRP =
tRP(IDD); CKE is HIGH, CS is HIGH between valid commands.
Address inputs are switching; Data Bus inputs are switching;
1431
mA
Operating Burst
Read Current
I
DD
4R
Burst Read: All banks open; Continuous burst reads; BL = 4; AL =
0, CL = CL(IDD; tCK = tCK(IDD; tRAS =tRAS.MAX.(IDD, tRP =
tRP(IDD; CKE is HIGH, CS is HIGH between valid commands.
Address inputs are switching; Data Bus inputs are switching;
IOUT = 0 mA.
1324
mA
Burst Refresh
Current
I
DD
5
Refresh command at every 7.8 us; CKE is HIGH, /CS is HIGH
between valid commands; Other control and address bus inputs
are switching; Data bus inputs are switching.
2160
mA
Self Refresh
Current
I
DD
6
CK and /CK at 0 V; CKE ≤ 0.2 V; Other control and address bus
inputs are floating; Data bus inputs are floating.
270
mA
Operating Bank
Interleave Read
Current
I
DD
7
All bank interleaving reads, I
OUT
= 0 mA; BL = 4, CL = 5 t
CK
;
AL = 70 ns; t
RRD
= 7.5 ns; CKE is HIGH, /CS is HIGH between
valid commands; Address bus inputs are stable during deselects;
Data bus inputs are switching.
2360
mA
Notes: 1. For all I
DD
X measurements, t
CK
= 3 ns, t
RC
= 60 ns, t
RCD
= 15 ns, t
RAS
= 45 ns, and t
RP
= 15 ns unless otherwise specified.
2. All I
DD
X values shown are worst-case maximums, considering all DRAMs, Register, and the PLL.