Datasheet

DTM63356H
4 GB - 240-Pin Registered DDR2 DIMM ECC with CMD/ADD Parity
Document 06120, Revision A, 16-Feb-11, Dataram Corporation 

 2011 Page 8
SERIAL PRESENCE DETECT MATRIX
Byte# Function. Value Hex
0 Number of Bytes Utilized by Module Manufacturer
128 bytes
80
1
Total number of Bytes in SPD device
256 bytes
08
2
Memory Type
DDR2
SDRAM
08
3
Number of Row Addresses
14 0E
4
Number of Column Addresses
11 0B
Module Attributes - Number of Ranks, Package and Height 61
# of Ranks - 2
Card on Card - No
DRAM Package - Planar
5
Module Height - 30mm
6
Module Data Width.
72 48
7
Reserved
UNUSED 00
8
Voltage Interface Level of this assembly
SSTL/1.8V
05
9
SDRAM Cycle time. (Max. Supported CAS latency). CL=X (tCK) ns
3 30
10
SDRAM Access from Clock. (Highest CAS latency). (tAC) ns
0.45 45
DIMM configuration type (Non-parity, Parity or ECC)
06
Data Parity -
Data ECC - X
Address/Command Parity - X
TBD -
TBD -
TBD -
TBD -
11
TBD -
12
Refresh Rate/Type (µs)
7.8 (SR)
82
13
Primary SDRAM Width
4 04
14
Error Checking SDRAM Width
4 04
15
Reserved
UNUSED 00
SDRAM Device Attributes: Burst Lengths Supported
0C
TBD -
TBD -
Burst Length = 4 - X
Burst Length = 8 - X
TBD -
16
TBD -