Datasheet

DTM63356H
4 GB - 240-Pin Registered DDR2 DIMM ECC with CMD/ADD Parity
Document 06120, Revision A, 16-Feb-11, Dataram Corporation 

 2011 Page 10
25 Minimum Clock Cycle Time at CL = X-2 (ns) 0.50 50
26 Maximum Data Access Time (tAC) from Clock at CL = X-2 (ns) 0.50 60
27 Minimum Row Precharge Time (tRP) (ns) 15 3C
28 Minimum Row Active to Row Active Delay (tRRD) (ns) 7.5 1E
29 Minimum RAS to CAS Delay (tRCD) (ns) 15 3C
30 Minimum Active to Precharge Time (tRAS) (ns) 45 2D
31 Module Rank Density
2GB
02
32 Address and Command Setup Time Before Clock (tIS) (ns) 0.2 20
33 Address and Command Hold Time After Clock (tIH) (ns) 0.27 27
34 Data Input Setup Time Before Strobe (tDS) (ns) 0.1 10
35 Data Input Hold Time After Strobe (tDH) (ns) 0.17 17
36 Write Recovery Time (tWR) (ns) 15 3C
37 Internal write to read command delay (tWTR) (ns) 7.5 1E
38 Internal read to precharge command delay (tRTP ) (ns) 7.5 1E
39 Memory Analysis Probe Characteristics. UNUSED 00
Extension of Byte 41(tRC) and Byte 42 (tRFC) (ns)
06
Add this value to byte 41 - 0
40
Add this value to byte 42 - 0.5
41 SDRAM Device Minimum Active to Active/Auto Refresh Time (tRC) (ns) 60 3C
42
SDRAM Device Minimum Auto-Refresh to Active/Auto-Refresh
Command Period (tRFC). (ns)
127.5 7F
43 SDRAM Device Maximum Cycle Time (tCK max). (ns) 8 80
44 SDRAM Dev DQS-DQ Skew for DQS & DQ signals (tDQSQ) (ns) 0.24 18
45 DDR SDRAM Device Read Data Hold Skew Factor (tQHS) (ns) 0.34 22
46 PLL Relock Time (µs) 15 0F
DRAM maximun Case Temperature Delta. (C). 00
DT4R4W Delta (Bits 0:3) - 0
47
Tcasemax delta (Bits 7:4) - 0
48
Thermal Resistance of DRAM Package from Top (Case) to Ambient (Psi T-A
DRAM). (C/Watt)
0 00
DRAM Case Temperature Rise from Ambient due to Activate-Precharge/
Mode Bits (DT0/Mode Bits). (C).
00
Bit 0. If "0" DRAM does not support high temperature self-refresh entry - 1
Bit 1. If "0" Do not need double refresh rate for the proper operation - 0
49
DT0, (Bits 2:7) - 0