Datasheet
DTM63323
1 GB - 128Mx64, 240-Pin Unbuffered DDR2 DIMM
Document 06813, Revision F, 07-JAN-10, Dataram Corporation © 2010 Page 9
Latency = 5 - X
19 DIMM Mechanical Characteristics. Max. module thickness. (mm) x </= 4.10 0x01
DIMM type information 0x02
Regular RDIMM (133.35mm) -
Regular UDIMM (133.35mm) - X
SODIMM (67.6mm) -
Micro-DIMM (45.5mm) -
Mini RDIMM (82.0mm) -
Mini UDIMM (82.0mm) -
TBD -
20
TBD -
SDRAM Module Attributes (Refer to Byte20 for DIMM type information). 0x00
Number of active registers on the DIMM (N/A for UDIMM) - 1
Number of PLL on the DIMM (N/A for UDIMM) -
0
21 FET Switch External Enable - No
TBD -
Analysis probe installed - No
TBD -
SDRAM Device Attributes: General 0x03
Includes Weak Driver - X
50 ohm ODT - X
TBD -
TBD -
TBD -
TBD -
TBD -
22
TBD -
23 Minimum Clock Cycle Time at Reduced CAS Latency, CL = X-1 (ns) 3.75 0x3D
24 Maximum Data Access Time (tAC ) from Clock at CL = X- 1 (ns) 0.45 0x45
25 Minimum Clock Cycle Time at CL = X-2 (ns) 5 0x50
26 Maximum Data Access Time (tAC ) from Clock at CL = X-2 (ns) 0.45 0x45
27 Minimum Row Precharge Time (tRP ) (ns) 15 0x3C
28 Minimum Row Active to Row Active Delay (tRRD ) (ns) 7.5 0x1E
29 Minimum RAS to CAS Delay (tRCD ) (ns) 15 0x3C
30 Minimum Active to Precharge Time (tRAS ) (ns) 45 0x2D
31 Module Rank Density 512MB 0x80
32 Address and Command Setup Time Before Clock (tIS) (ns) 0.2 0x20
33 Address and Command Hold Time After Clock (tIH) (ns) 0.27 0x27