Datasheet

DTM63310
1 GB - 128Mx72, 240-Pin Registered DDR2 DIMM
Document 06454, Revision E, 24-MAR-08, Dataram Corporation © 2008 Page 9
25 Minimum Clock Cycle Time at Reduced CAS Latency CL = X-2 5 50
26 Maximum Data Access Time (t
AC
) from Clock at CL = X-2 0.6 60
27 Minimum Row Precharge Time (t
RP
) 15 ns 3C
28 Minimum Row Active to Row Active Delay (t
RRD
) 7.5 ns 1E
29 Minimum RAS to CAS Delay (t
RCD
) 15 ns 3C
30 Minimum Active to Precharge Time (t
RAS
) 45 ns 2D
31 Module Rank Density 1 GB 01
32 Address and Command Setup Time before Clock (t
IS
) 0.50 ns 50
33 Address and Command Hold Time after Clock (t
IH
) 0.50 ns 50
34 Data Input Setup Time before Strobe (t
DS
) 0.15 ns 15
35 Data Input Hold Time after Strobe (t
DH
) 0.28 ns 28
36 Write Recovery Time (t
WR
) 15 ns 3C
37 Internal Write-to-Read Command Delay (t
WTR
) 10 ns 28
38 Internal Read-to-Precharge Command Delay (t
RTP
) 7.5 ns 1E
39 Memory Analysis Probe Characteristics. UNUSED 00
40 Extension of Byte 41(t
RC
) and Byte 42 (t
RFC
) 00
Add this value to byte 41 0 ns
Add this value to byte 42 0 ns
41 Minimum Active-to-Active / Auto Refresh Time (t
RC
) 60 ns 3C
42 Minimum Auto-Refresh to Active/Auto-Refresh Command Period (t
RFC
) 105 ns 69
43 Maximum Cycle Time (t
CK
max) 8 ns 80
44 DQS-DQ Skew for DQS & associated DQ Signals (t
DQSQ
) 0.35 ns 23
45 Read Data Hold Skew Factor (t
QHS
) 0.45 ns 2D
46 PLL Relock Time 15 μs 0F
47-61 Reserved UNUSED 00
62 SPD Revision Revision 1.0 10
63 Checksum for Bytes 0-62 checksum F2
64 Module Manufacturer’s JEDEC ID Code Dataram ID 7F
65 Module Manufacturer’s JEDEC ID Code Dataram ID 91
66-71 Module Manufacturer’s JEDEC ID Code UNUSED 00
72 Module Manufacturing Location UNUSED 00
73-90 Module Part Number UNUSED 00
91-92 Module Revision Code UNUSED 00
93-94 Module Manufacturing Date UNUSED 00
95-98 Module Serial Number [serial number]
99-127 Manufacturer’s Specific Data UNUSED 00