Datasheet
DTM63310
1 GB - 128Mx72, 240-Pin Registered DDR2 DIMM
Document 06454, Revision E, 24-MAR-08, Dataram Corporation © 2008 Page 8
Serial Presence Detect Contents
Byte# Function Value Hex
0 Number of Serial PD Bytes written during module production 128 bytes 80
1 Total number of Bytes in Serial Presence Detect device 256 bytes 08
2 Fundamental Memory Type DDR2 08
3 Number of Row Addresses 14 0E
4 Number of Column Addresses 11 0B
5 Module Attributes - Number of Ranks, Package and Height 60
bits 0 through 2 - number of Ranks 1
bit 3 - Card on Card No
bit 4 - DRAM Package Planar
bits 5 through 7 - Module Height 30mm
6 Module Data Width 72 48
7 Reserved UNUSED 00
8 Voltage Interface Level of this assembly SSTL/1.8V 05
9 SDRAM Cycle time at highest CAS Latency 5 ns 50
10 SDRAM Access from Clock time at highest CAS Latency (t
AC
) 0.6 ns 60
11 DIMM configuration type ECC 02
12 Refresh Rate/Type
7.8 μs
Self Refresh
82
13 Primary SDRAM Width 4 04
14 Error Checking SDRAM Width 4 04
15 Reserved UNUSED 00
16 SDRAM Device Attributes - Burst Lengths Supported 0C
bits 0 and 1 - [undefined]
bit 2 - Burst Length = 4 yes
bit 3 - Burst Length = 8 yes
bits 4 through 7 - [undefined]
17 SDRAM Device Attributes - Number of Banks on SDRAM Device 4 04
18 SDRAM Device Attributes - CAS Latency 38
bits 0 and 1 - [undefined]
bit 2 - Latency = 2
bit 3 - Latency = 3 yes
bit 4 - Latency = 4 yes
bit 5 - Latency = 5 yes
bits 6 and 7 - [undefined]
19 Reserved UNUSED 00
20 DIMM type information 01
bit 0 - Regular RDIMM (133.35mm) yes
bit 1 - Regular UDIMM (133.35mm) no
bit 2 - SODIMM (67.6mm) no
bit 3 - Micro-DIMM (45.5mm) no
bit 4 - Mini RDIMM (82.0mm) no
bit 5 - Mini UDIMM (82.0mm) no
bits 6 and 7 - [undefined] no
21 Module Attributes 00
bits 0 through 3 - [undefined]
bit 4 - FET Switch External Enable no
bit 5 - [undefined]
bit 6 - Analysis probe installed no
bit 7 - [undefined]
22 SDRAM Device Attributes - General 00
bit 0 - Supports Weak Driver no
bits 1 through 7 - [undefined]
23 Minimum Clock Cycle Time at Reduced CAS Latency, CL = X-1 5 ns 50
24 Maximum Data Access Time (t
AC
) from Clock at CL = X-1 0.6 ns 60