Integration Guide

Engine Video Format
36 DE2011-DL
Output Data Timing
The data output of the sensor is synchronized with the PIXCLK output.
When LINE_VALID (LV) is HIGH, one 10-bit pixel datum is output every PIX-
CLK period. Figure 14 shows an example of pixel data timing, and Figure 15
shows basic timing for a complete frame readout.
Figure 14. Timing example of pixel data
Figure 15. Row Timing and FRAME_VALID/LINE_VALID Signals
A Active data time Sensor register defined 752 28.20us
P1 Frame start blanking Sensor register defined 71 2.66us
P2 Frame end blanking 23 (fixed) 23 0.86us
Q Horizontal blanking Sensor register defined 94 3.52us
A+Q Row time A+Q 846 31.72us
V Vertical blanking
Sensor register defined 37,228 1.39ms
Nrows(A+Q) Frame valid time
Sensor register defined 406,080 15.23ms
F Total frame time
V+(Nrows(A+Q)) 443,308 16.62ms
Sensor Registers Settings
For information on register settings, refer to the Aptina MT9V024 mono-
chrome WVGA Image Sensor Datasheet, available at http://www.aptina.com.
Parameter Name Equation Pixel Clock
Timing at
26,66MHz