User's Manual

Datalogic Scanning, Inc
959 Terry Street
Eugene, Oregon 97402
Page 97 10/23/2009
Revision X2
PSKEY_TEMPERATURE_VS_DELTA_TX_BB_MR_HEADER.
The basic rate setting is controlled by PSKEY_ANALOGUE_ATTENUATOR.
(The abbreviation MR for Medium Rate is used consistently in place of EDR for Enhanced Data Rate
throughout the PS keys as many were introduced before the abbreviation EDR came into use.)
Key Name Key Number Type Default Setting
PSKEY_AMUX_CLOCK 0x0398 uint16 AMUX_CLK_OFF
This PSKEY controls the frequency of the clock available through the analogue multiplexer. To use this
control, the chip must have the AMUX clock deglitcher circuit and PSKEY_AMUX_AIO0
must be set to
'AMUX'.
The drop-down box options in this control are only correct for BC4-Headset, BC4_Audio Flash. Other
chips may not output the advertised clock or may only output a subset of the clocks.
Key Name Key Number Type Default Setting
PSKEY_PIO_WAKEUP_STATE 0x039f uint16 0xFFFF
Controls the state for each PIO line (0 to 15) that will wake the chip from deep sleep. Each bit corresponds
to a PIO line. Setting a bit high will result in the chip waking when that line goes high, setting the bit low
will cause the chip to wake when the line goes low. The PIO lines must already have been configured to
wake the chip using either PSKEY_DEEP_SLEEP_PIO_WAKE
or the VM.
Key Name Key Number Type Default Setting
PSKEY_PROG_BRANCH_MODE 0x03a1 uint16 3
The branch prediction mode to use for the program memory.
This PSKEY should only be changed on advice from CSR.
Key Name Key Number Type Default Setting
PSKEY_PROG_WAIT_STATES 0x03a2 uint16 1
The number of wait states to use for the program memory.
This pskey should only be changed on advice from CSR.
Key Name Key Number Type Default Setting
PSKEY_TX_PRE_LVL_CLASS1 0x03a8 uint8 8
Sets the level of the transmitter pre-amplifier when used with class 1 operation. Otherwise the same as
PSKEY_TX_PRE_LVL
.
Key Name Key Number Type Default Setting
PSKEY_RX_MR_EQ_TAPS 0x03a9 uint16[] 0x1AB2, 0x0F1C, 0x1D11,
0x2BD3
Set the default value for the four RX_MR_EQ_TAPS configuration registers used for Enhanced Data Rate