User's Manual

Datalogic Scanning, Inc
959 Terry Street
Eugene, Oregon 97402
Page 74 10/23/2009
Revision X2
Larger values than necessary have been observed to produce additional phase noise.
Direct measurement using an oscilloscope is not recommended because the additional load capacitance can
disrupt operation of the oscillator and the device's internal measurements.
Note that this key is not used during DFU. In that mode the crystal bias is always set to maximum.
Key Name Key Number Type Default Setting
PSKEY_PCM_MIN_CPU_CLOCK 0x024d uint16 CPU_SLOW_4M
The firmware tries to save power by reducing the clock rate when the processor is idle. The clock drives the
CPU, PCM, UART, USB, baseband hardware, etc. This is normally called "shallow sleep."
Some of the chip's hardware sets a lower limit on how slowly the clock can be run. This key controls what
limit PCM bus activity places on the clock speed.
The default value of 4MHz is suitable for many PCM operations. It may be necessary to increase this for
high sample rates and certain operating modes. It may be possible to reduce this value for reduced power
consumption, but the PCM function may not operate correctly if run too slow. For more advice, contact
CSR.
The pskey's acceptable values are:
0 CPU_FAST (full rate)
1 CPU_SLOW_4M (4 MHz)
2 CPU_SLOW_2M (2 MHz)
3 CPU_SLOW_1p024M (1.024 MHz)
See also PSKEY_CODEC_MIN_CPU_CLOCK
.
Key Name Key Number Type Default Setting
PSKEY_CPU_IDLE_MODE 0x0251 cpu_idle_mode cpu_idle_ram
When the radio is active but the chip is otherwise idle, background processor activity can be limited in
various ways. Which is most apppropriate depends on details of the hardware. Hence this key should not be
altered without appropriate knowledge. The possibilities are
NONE (0): Processor continues normal task loop
LONG_LOOP (1): Processor executes long idle loop
SHORT_LOOP (2): Processor executes short idle loop
RAM (3): Processor idles in RAM
ROM (4): Processor idles in ROM
Key Name Key Number Type Default Setting
PSKEY_DEEP_SLEEP_CLEAR_RTS 0x0252 bool FALSE
This key is used for deep sleep with the BCSP and H5 host transports only. If TRUE, the chip clears the
RTS line (i.e. sets it high) when it enters deep sleep, and (depending on the state of the UART) may reset it
afterwards if it is ready to receive.
If hardware flow control is in effect on the remote host, setting the key causes the remote UART not to
transmit packets while the chip is in deep sleep. Therefore it is not possible to use the effect of BCSP