User's Manual

Datalogic Scanning, Inc
959 Terry Street
Eugene, Oregon 97402
Page 69 10/23/2009
Revision X2
Applies when the host interface is BCSP, TWUTL or VM access to the UART, and depends on the key
PSKEY_DEEP_SLEEP_STATE being set to allow deep sleep. If we have had no transmission from the
host for at least this number of milliseconds, and we have no data to send, then we may go into deep sleep,
depending on restrictions from any other source. Setting the value to 0 inhibits deep sleep for BCSP,
TWUTL or VM UART access, but has no effect if another host interface is in use.
The default BCSP/TWUTL retransmit period is 0.25 seconds, so setting this value less than that, but non-
zero, is probably a bad idea.
With BCSP or TWUTL, any data on the UART will wake the chip from deep sleep. However the particular
transmission that woke it will be lost. The chip will wake up about 5ms later.
Key Name Key Number Type Default Setting
PSKEY_DEEP_SLEEP_STATE 0x0229 deep_sleep_state DEEP_SLEEP_ALWAYS
BlueCore has two types of low power state. The one which allows the more saving, and hence has the more
constraints on its use, is referred to as "deep sleep" and may be configured by this key.
Type deep_sleep_state can be treated as a uint16, taking these values:
NEVER (0): Deep sleep will never be used.
ALWAYS (1): Deep sleep will be used whenever possible.
INACTIVE (2): Deep sleep when there are no ACL
connections.
ALWAYS_ACCURATE (3): Deep sleep will be used whenever possible;
the firmware assumes the module has an
accurate external slow clock which does not
need calibrating after startup.
If the setting is ACCURATE (3), PSKEY_DEEP_SLEEP_USE_EXTERNAL_CLOCK
should be set to
TRUE to indicate that an external slow clock is in use. This combination of settings saves power as the
firmware will not need to calibrate the slow clock against the standard 20 ppm clock once the frequency of
the external slow clock has been ascertained.
In deep sleep, BlueCore's accurate clock is not operational and timing is maintained by a low power but
less accurate clock. Deep sleep may be entered when an ACL connection is in hold, sniff or park mode;
hence accuracy is lost. In certain situations, where power saving is not a major priority but maintaining
accuracy of the clock is (for example, a network access point which has a large number of parked
connections), it may be advantageous to disable deep sleep mode with this key.
Note that changing this PSKEY has implications for the setting of PSKEY_DEVICE_DRIFT
. See the
description of that key for details.
Deep sleep also causes slightly slower response on the UART when BCSP is in use if no data has been
received for a while. See PSKEY_UART_SLEEP_TIMEOUT
.
This does not affect the other low power states, in which clock accuracy is not lost.
Key Name Key Number Type Default Setting
PSKEY_IQ_ENABLE_PHASE_TRIM 0x022d bool TRUE