User's Manual

Datalogic Scanning, Inc
959 Terry Street
Eugene, Oregon 97402
Page 103 10/23/2009
Revision X2
parameter but with greater resolution.
Key Name Key Number Type Default Setting
PSKEY_TRIM_RADIO_FILTERS 0x03c2 uint16 48
This key should only be altered on advice from CSR.
If bit 0 is set, the chip will perform a long (approximately 80 ms) trim of the radio's transmit and receive
filters at boot, and periodically a short update. This is not supported in firmware which supports enhanced
data rate.
If bit 1 is set, the chip will automatically determine a suitable value for the RSSI range on receive to
prevent the receiver from saturating. (This affects the value originally set by PSKEY_RSSI_HI_TARGET
or by PSKEY_LC_RSSI_GOLDEN_RANGE
on builds without PSKEY_RSSI_HI_TARGET).
If bit 2 is set, the chip will dynamically configure the DC offset in the transmit baseband at startup. This
only applies to BlueCore2: this feature is always enabled on BlueCore3.
In builds with PSKEY_MR_RX_FILTER_RESPONSE key present, bit 3 is used to enable a receive filters
trim for use with Enhanced Data Rate (EDR). An initialisation value given by
PSKEY_MR_RX_FILTER_TRIM which must also be present.
If the PSKEY_MR_RX_FILTER_RESPONSE key is not present, bit 3 has no function. The newer the
golden curve trim can be enabled when present by setting the
MR_ENABLE_RX_GOLDEN_CURVE_TRIM pskey to true.
If bit 4 is set in builds with PSKEY_MR_ENABLE_RX_GOLDEN_CURVE_TRIM
from BlueCore 5
onwards then the golden curve RX filter trim will be be performed periodically.
If bit 5 is set in builds with PSKEY_MR_ENABLE_RX_GOLDEN_CURVE_TRIM
from BlueCore 5
onwards then the golden curve RX filter trim value will also be used for basic rate reception. If 0 then the
default value used will be as defined by PSKEY_ANA_RX_FTRIM
.
If bit 6 is set in builds with PSKEY_MR_ENABLE_RX_GOLDEN_CURVE_TRIM from BlueCore 5
onwards then the "best of 5" enhancement will be disabled.
Key Name Key
Number
Type Default Setting
PSKEY_DEEP_SLEEP_USE_EXTERNAL_CLOCK 0x03c3 bool FALSE
Versions of BlueCore from BlueCore3 can take a 32 kHz clock input to AIO0 to act as a timing source
when the chip is in deep sleep. (This is referred to as the slow clock.) Its frequency must be stable to at
least 250 parts per million. Its use is enabled by setting this key to TRUE.
The clock does not have to be exactly 32 kHz; anything within a few percent (including 30 kHz) is useful.
The firmware will calibrate this external slow clock against the standard 20 ppm clock (as supplied by
crystal or TCXO) at startup. If PSKEY_DEEP_SLEEP_STATE
is set to
DEEP_SLEEP_ALWAYS_ACCURATE, the firmware will assume the external slow clock does not need
subsequent calibration, saving extra power.
If the worst-case accuracy of the supplied clock is significantly better than 250 parts per million,