Product manual

Product Manual - DM991 Series V Family - 204.4092.08 17
In the activation stage, the DSL interface LED blinks once a second (on and off times are equal).
3.4. Data Mode
This is the final stage, where the modem transmits data normally. It will use the final G.shdsl frame,
sending information as negotiated during handshake and using the coefficients that were calculated after
the transmission line was evaluated during the training period.
Whenever the interface is in sync, the DSL status LED will remain on.
3.4.1. G.shdsl Frame Structure
The G.shdsl frame has four data blocks (payload blocks) that are separated by the header bits. The
header repeats itself each 6ms, regardless of the configured rate.
The header has an essential function for data transmission, for it ensures alignment, it transports
management information through EOC (Embedded Operations Channel) and it also has a data error
identification mechanism (CRC6).
The frame G.shdsl also allows to transmit CAS information (Channel Associated Signilling) from link E1.
. . .
O
H
O
H
O
H
O
H
TS
n
TS
1
TS
2
Stb
Sub-Block 1 Sub-Block 2 Sub-Block 3 Sub-Block 4 Sub-Block 5 Sub-Block 6 Sub-Block 7 Sub-Block 8 Sub-Block 9 Sub-Block 10 Sub-Block 11 Sub-Block 12
Frame
Sync
Payload
Block
Payload
Block
Payload
Block
Payload
Block
Payload Data, Bits 1
to
k
s
Figure 11. G.shdsl frame order diagram with CAS signaling
The sub block size varies according to the number of channels. Each sub block has Nx8 bits, where N is
the number of channels that was negotiated during handshake.
Timeslots E1 V.35 Nx64 kbit/s Ethernet Idle CAS
Figure 12. G.shdsl frame order diagram with CAS signaling
The frame structure that is sent and received by the G.shdsl modem consists in the E1 timeslots, in the
V.35 channel at Nx64k, in the Ethernet channel at Nx64kbit/s, in empty timeslots (idle) for filling the
installed modem rate and in a CAS timeslot, in this order.