Specifications

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Si5040

10 Gbps XFP TRANSCEIVER WITH JITTER ATTENUATOR

Features

Complete, high-performance, low-power, 10 Gbps XFP transceiver featuring

independent CDRs, DSPLL

-based jitter-attenuating CMUs, and data retimers in both

transmit and receive directions.

Applications

Description

The Si5040 is a complete, low-power, high-performance XFP transceiver suitable for

multiple XFP module types, from short-reach datacom to long-reach telecom

applications. The Si5040 integrates a rate-agile, programmable-bandwidth, jitter-

attenuating CMU in the transmit direction, which significantly attenuates jitter present at

the XFI interface and on the applied reference clock, removing the need for an external

jitter cleanup circuit. The device supports referenceless operation or operation with a

synchronous or asynchronous reference clock. The device can be completely configured

through a serial microcontroller interface. The Si5040 is compliant with all XFP

requirements in both datacom and telecom applications. The Si5040 is packaged in a

5x5 mm LGA package and dissipates 575 mW (typ).

Functional Block Diagram

 DSPLL-based, jitter-attenuating CMUs

in both transmit and receive directions

 Frequency-agile jitter filtering from 9.8 to

11.35 Gbps (continuous)

 Compliant to XFP specifications and

jitter specifications for telecom

(SONET/SDH, OTU-2) and datacom

(10 GbE/10 GbE+FEC and

10 GFC/10 GFC+FEC) applications

 Supports referenceless operation

 Integrated limiting amplifier provides

better than 8 mV receiver sensitivity

 User-programmable receiver loss-of-

signal (LOS) detector

 Transmitter jitter generation 2.5 mUI

rms

(typical)

 Automatic slicing level adjustment with

optional programmable override

 Programmable sample phase

adjustment

 Line loopback, XFI loopback, pattern

generation, and pattern check test

capabilities

 1.8/3.3 V or single 1.8 V supply

 575 mW (typ) power dissipation

 5x5 mm LGA package

 Serial microcontroller interface control

 XFP telecom modules

 XFP datacom modules

 Optical test equipment

 Jitter-attenuation and signal

regeneration of 10 Gbps serial signal

on line cards

CDR

DSPLL

Jitter Attenuator

CDR Equalizer

DSPLL

Jitter Attenuator

RXDIN RD

RefCLK

(optional)

TXDOUT

RX_LOS

Clk

FIFO

CML

Clk

Serial

Port

Serial

Interface

Control

Interrupt

XFI

Loopback

RX_LOL

Line

Loopback

Program

mable

Equalizer

Ordering Information:

See page 103.

Pin Assignments

Si5040

(Transparent Top View)

Si5100

GND

PAD

2526272829303132

VDDIO

GND

RXDIN+

RXDIN–

GND

TXDOUT+

TXDOUT–

GND

RD+

GND

TD–

GND

SCK

9 10 11 12 13 14 15 16

TD+

RD–

GND

REFCLK+

SPSEL

REFCLK-

INTERRUPT

RX_LOL

RX_LOS

GND

PAD

GND

PAD

GND

PAD

Summary of content (108 pages)

PAGE 1
Si5040 10 Gbps XFP T RANSCEIVER W I T H J I T T E R A TTENUATOR Features Complete, high-performance, low-power, 10 Gbps XFP transceiver featuring independent CDRs, DSPLL®-based jitter-attenuating CMUs, and data retimers in both transmit and receive directions.
PAGE 2
Si5040 2 Rev. 1.
PAGE 3
Si5040 TABLE O F C ONTENTS Section Page 1. Si5040 Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 4
Rev. 1.3 TXDOUT- TXDOUT+ RXDIN+ RXDIN- CML RX CDR TX FIFO LTR REFCLK INTERRUPT Interrupt Control Line LB Data XFI LB Data TM DLOS SQM TX LOS SCK SD SS SPISEL TXLOL refLOS REFCLK Equalizer LVPECL CML Line LB Data RX Pattern Gen.
PAGE 5
Si5040 2. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Symbol Min1 Typ Max1 Unit TA –40 25 95 C Supply Voltage VDD2 1.62 1.80 1.89 V LVTTL I/O Supply Voltage VDDIO 1.62 — 3.63 V Ambient Temperature Test Condition Notes: 1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 C unless otherwise stated. 2.
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Si5040 Table 2. DC Characteristics (VDD = 1.8 V +5%/–10%, TA = –40 to 95 °C) Parameter Supply Current Power Dissipation Symbol Test Condition Min Typ Max Unit — — 370 mA VDD = 1.89 V1 VDD = 1.8 V1 — — — 575 700 — mW IDD PD Differential Input Voltage Swing (RXDIN) (at BER 10–12) VID Figure 1 with Receive Equalizer bypassed 8 — 1000 mVPPD Common Mode Output Voltage (TXDOUT) VOCM Figure 1 — 1.
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Si5040 Table 2. DC Characteristics (Continued) (VDD = 1.8 V +5%/–10%, TA = –40 to 95 °C) Parameter Symbol Test Condition Min Typ Max Unit V I2C Bus Lines (SD, SCK) Input Voltage Low VILI2C — — 0.3 x VDDIO Input Voltage High VIHI2C 0.7 x VDDIO — — Input Current Hysteresis of Schmitt trigger inputs Output Voltage Low III2C VIN = 0.1 x VDDIO to 0.9 x VDDIO –10 — 10 VHYSI2C VDDIO = 1.8 V 0.1 x VDD — — VDDIO = 3.3 V 0.05 x VDD — — VDDIO = 1.8 V IO = 3 mA — — 0.
PAGE 8
Si5040 Table 3. AC Characteristics–RXDIN (Receiver Input) (VDD = 1.8 V +5/–10%, TA = –40 to 95 C) Parameter Symbol Test Condition Min Typ Max Unit 9.80 9.95 11.35 Gbps < 2 GHz 5 GHz 10 GHz 15 10 5 — — — — — — dB dB dB ALOS Range Analog Mode 10 — 400 mVPPD ALOS Step Size Analog Mode — 1 — mVPPD ALOS Relative Accuracy Analog Mode 1 — — mV DLOS Range Consecutive Digits Mode 0.5 — 100 µs DLOS Accuracy Consecutive Digits Mode 0.
PAGE 9
Si5040 Table 4. AC Characteristics—RD (Receiver Output) (VDD = 1.8 V +5/–10%, TA = –40 to 95 C) Parameter Symbol Test Condition Common Mode AC Output Voltage Output Rise and Fall Times (RD) Min Typ Max Unit — — 15 mVRMS tR,tF Figure 2 24 — — ps SDD22 0.05–0.1 GHz 20 — — dB 0.1–5.5 GHz 8 — — dB 5.5–12 GHz * — — dB SCC22 0.1–15 GHz 3 — — dB Deterministic Jitter DJ — — 0.09 UIPP Total Jitter TJ >4 MHz. See Appendix E1 in the XFP specification. — — 0.
PAGE 10
Absolute Amplitude Si5040 Y2 Y1 0 –Y1 –Y2 0.0 X1 X2 1–X2 1–X1 Normalized Time (UI) Figure 3. Receiver Differential Output Mask (RD) 10 Rev. 1.3 1.
PAGE 11
Si5040 Table 5. AC Characteristics—TXDOUT (Transmitter Output) (VDD = 1.8 V +5/–10%, TA = –40 to 95 C) Parameter Output Rise + Fall Times Symbol Test Condition Min Typ Max Unit tR, tF Figure 2 20 25 30 ps 400 kHz–10 GHz 10 GHz–16 GHz 6 4 — — — — dB dB Output Return Loss Random RMS Jitter Generation, TXDOUT1 JGEN(rms) OC-192, CMU mode 0 — 2.8 4.6 mUIRMS Total Peak-to-Peak Jitter Generation, TXDOUT1 JGEN(PP) OC-192, CMU mode 0 — 36 60 mUIPP — 180 220 Hz — 1.37 1.
PAGE 12
Si5040 Table 6. AC Characteristics–TD (Transmitter Input) Parameter Symbol Test Condition Min Typ Max Unit 9.80 9.95 11.35 Gbps 0.05–0.1 GHz 20 — — dB 0.1–5.5 GHz 8 — — dB 5.5–12 GHz See Note 1 — — dB 0.1–15 GHz 3 — — dB — 0.45 UIPP — 0.
PAGE 13
Si5040 Si5040 TD Jitter Tolerance (Typ) 100 XFI Specification 1 0.1 0.01 1 10 100 1000 10000 100000 1000000 10000000 100000000 Frequency (Hz) Figure 4. XFI Sinusoidal Jitter Tolerance (UIPP) Absolute Amplitude Sinusoidal Jitter Tolerance (UIpp) 10 Y2 Y1 0 –Y1 –Y2 0.0 X1 1–X1 1.0 Normalized Time (UI) Figure 5. Transmitter Differential Input Mask (TD) Rev. 1.
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Si5040 Table 8. AC Characteristics—I2C Bus Lines (SD, SCK) (VDD = 1.8 V +5/–10%, TA = –40 to 95 C) Parameter Pin Capacitance Symbol Test Condition CII2C Min Typ Max Unit — — 10 pF Table 9. Switching Characteristics—Serial Microcontroller Interface2 VDD = 1.8 V +5/–10%, VDDIO = 3.
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Si5040 tc tr tf SCK thsc tlsc tsu1 th1 SS tcs tsu2 th2 SD td1 td3 td2 SD Figure 6. Serial Microcontroller Interface Timing Diagram SS SCK SD 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 2 1 0 Figure 7. SPI-Like Interface Write/Set Address Command SS SCK SD 7 6 5 4 3 2 1 Read Command 0 7 6 5 4 3 Read Data Figure 8. SPI-Like Interface Read Command Rev. 1.
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Si5040 Table 10. Thermal Characteristics Parameter Thermal Resistance Junction to Ambient Symbol Test Condition Value Unit JA Still Air 50 C/W Symbol Value Unit VDD –0.5 to 1.98 V VDDIO –0.5 to 3.8 V VDIF –0.3 to (VDD+ 0.3) V ±50 mA Table 11.
PAGE 17
Si5040 3. Typical Application Schematic TXDOUT+ .1 UF .1 UF VDD_1P8 VDD_1P8 VDD_1P8 .01 UF .01 UF 4VDDIO SD25 SS26 VDD327 GND728 TD-21 U? 16INTRPT 15VDD1 14REFCLK- 12VDD2 13REFCLK+ 11NC TD- .1 UF RD- GND617 .1 UF RD+ .01 UF VDD_1P8 REFCLK+ Rev. 1.3 .01 UF VDD_1P8 .01 UF .1 UF 9SPSEL RD-18 10NC RD+19 7RXDIN+ 8GND3 TD+ GND520 6RXDIN- .01 UF RXDIN+ .1 UF .1 UF TD+22 SI5040 5GND2 .1 UF .
PAGE 18
Si5040 4. Functional Description The Si5040 XFP transceiver is a single-chip, bidirectional signal conditioner for use in XFP modules as defined by the XFP multi-source agreement. The Si5040 includes independent clock and data recovery units (CDRs) and frequency-agile, jitter-attenuating clock multiplier units (CMUs) in both receive and transmit directions. The receive path includes a limiting amplifier and a programmable equalizer for direct connection to an optical receiver transimpedance amplifier.
PAGE 19
Si5040 5. Receiver The Si5040 receiver includes a programmable equalizer, a high-sensitivity limiting amplifier, clock and data recovery unit (CDR), and a FIFO/retimer function. 5.1. Receive Equalizer Normalized Output Amplitude (dB) The RX equalizer is a programmable equalizer designed to boost the high-frequency components while attenuating the low-frequency components.
PAGE 20
Si5040 5.2. Limiting Amplifier The Si5040 incorporates a high-sensitivity differential limiting amplifier with sufficient gain to allow direct connection to a transimpedance amplifier. The amplifier has a guaranteed sensitivity of 8 mVppd. 5.3. Receive Amplitude Monitor The Si5040 limiting amplifier includes circuitry that monitors the amplitude of the receiver differential input signal (RXDIN). The amplitude value can be read from the Peakdet register (Register 16).
PAGE 21
Si5040 No >0 transition in a 1024-bit field Yes Increment Reset Counter Count Is Count > dLosClearThresh *16 +1 No Yes Clear dLos Figure 11. Algorithm to Clear dLOS The receiver may be programmed to perform any of the following consequent actions upon declaring RX_LOS: 1. Lock the receiver to the applied reference clock (lock to reference): ltrOnLOS bit in Register 7. 2. Assert receiver loss of lock (LOL): lolOnLOS bit in Register 7. 3.
PAGE 22
Si5040 LOS=1? Y Y LOLonLOS =0 and ltrOnLos=0? (Default) LOLonLOS =1 and ltrOnLos =0? LOLonLOS = 1 and ltrOnLos = 1? LOLonLOS = 0 and ltrOnLos = 1? Y Y CDR continuously tries to lock to incoming data, and the VCO frequency does not get re-centered prior to the lock acquisition process.
PAGE 23
Si5040 LOL=1? Y VCOCAL[1:0] = 01? VCOCAL[1:0] = 10 (Default)? VCOCAL[1:0] = 00? Y Y Is refClk present? N Y The internal VCO pull range will be automatically re-centered to the reference clock frequency to start the CDR lock acquisition process. The entire VCO frequency range will be swiped to start the CDR lock acquisition process. VCOCAL[1:0] = 11? Y Y Y Is refClk present? N VCO stays at the center of its frequency range awaiting for refClk Invalid mode! LOL will stay on. Figure 14.
PAGE 24
Si5040 5.6. Clock and Data Recovery (CDR) The Si5040 integrates a CDR to recover the clock and data from the input signal applied to RXDIN. The CDR can be operated with or without an external reference clock. Reference or referenceless operation is programmed in the RxCalConfig register (Register 8). If a reference clock is applied to the receiver, the CDR can be forced to lock to the reference clock in the event that a loss of signal occurs.
PAGE 25
Si5040 5.8.1.1. Dynamic Register Control The dynamic control of RxLoopFAcq (Register 98) is required to ensure the locking performance of the CDR. It is required for all applications that RxLoopFAcq be set to 98h when RX LOL is asserted and to 00h when RX LOL is deasserted. Only the default value and the value given above are supported for writes to Register 98. Any read back of this register will not necessarily return the value written.
PAGE 26
Si5040 aLOSThresh (Bit 1:0, Register 13 and Bit 7:0, Register 12) aLOSHyst[3:0] (Bit 7:4, Register 13) Peak-toPeak Monitor aLOS (Bit 1, Register 11) aLosEn (Bit 0, Register 10, Default= 1) RxdLosAssertThresh[7:0] (Bit 7:0, Register 17) RxdLosClearThresh (Bit 7:0, Register 18) DLOS Monitor 00: 01: 01: 01: LOS (Bit 5, Register 9, Bit 0, Register 11 or Pin 3) dLOS (Bit 2, Register 11) EN dLosEn[1:0] (Bit 2:1, Register 10) Disabled (Default) Based on consecutive number of 1s Based on consecutive number
PAGE 27
Si5040 TxdLosAssertThresh[7:0] (Bit 7:0, Register 145) TxdLosClearThresh (Bit 7:0, Register 146) dLosEn[1:0] (Bit 2:1, Register 138) dLOS (Bit 2, Register 139) DLOS Monitor LOS (Bit 5, Register 137 or Bit 0, Register 139) EN 00: Disabled (Default) 01: Based on consecutive number of 1s 01: Based on consecutive number of 0s 01: Based on either consecutive number of 1s or 0s TxSqmThresh[5:0] (Bit 7:2, Register 154) TxSqmDeassertThresh[5:0] (Bit 5:0, Register 155) 1 EN Signal Quality Monitor sqmAlarm
PAGE 28
Si5040 5.9. Receiver Phase Adjust The Si5040 receiver supports programmable sample phase adjust. The sampling point may be advanced or delayed in time by adjusting the value loaded into the RxPhaseAdjust register (Register 24). The range of adjustment is ±12 ps. 5.10. Receive Clock Multiplier Unit The Si5040 receiver incorporates a DSPLL®-based clock multiplier unit (CMU) that attenuates the jitter on data recovered from the line interface.
PAGE 29
Si5040 6. Transmitter The Si5040 transmitter includes an XFI-compliant, fixed-equalizer CDR for recovery of clock and data from the XFI channel (TD inputs), pattern generation and checking function (see “6.3. Clock and Data Recovery (CDR)”), transmit FIFO, and jitter-attenuating clock multiplier unit. 6.1. Transmitter Loss-of-Signal Alarm (LOS) The Si5040 transmitter generates a loss-of-signal alarm when the TD input signal fails to meet the selected programmable condition for Transmit Loss of Signal.
PAGE 30
Si5040 6.4. Transmitter Loss of Lock (LOL) Transmitter LOL functions in different ways depending on whether the transmitter is operating in reference or referenceless mode. By default (uselolmode Register 135, Bit 3 = 0), SQM-based LOL is used in referenceless mode, and Frequency-based LOL is used in reference mode. However, in reference mode, either SQM or Frequency LOL can be used by setting Register 135, Bits 2 and 3, to the appropriate values. 6.4.1.
PAGE 31
Si5040 6.7. Timing Modes Of Operation For maximum flexibility, the Si5040 supports three CMU timing modes that make it suitable for XFP modules targeted at both datacom and telecom applications. The modes of operation determine how the transmit CMU is configured. Timing modes are set in the TxCmuConfig register (Register 134). 6.7.1.
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Si5040 DSPLL ® Jitter Attenuator CMU XFI Recovered Clock TXDOUT CML CDR FIFO Equalizer XFI Recovered Data TD Figure 18. Referenceless Mode (Mode 0) DSPLL ® Jitter Attenuator CMU Synchronous Reference Clock XFI Recovered Clock TXDOUT CML CDR FIFO Equalizer XFI Recovered Data TD Figure 19. Synchronous Reference Clock (Mode 1) DSPLL® Jitter Attenuator CMU Cleaned Up Clock XFI Recovered Clock TXDOUT CML FIFO XFI Recovered Data Figure 20. Mode 2 32 Rev. 1.
PAGE 33
Si5040 7. Loopback Modes The Si5040 supports XFI Loopback, Lineside Loopback, and Looptime modes. 7.1. XFI Loopback The Si5040 is configured in the XFI Loopback mode by writing to the ChipConfig1 register (Register 2). The Si5040 is configured in the XFI Loopback mode by writing to the ChipConfig1 register (Register 2). Data on the TD input is retimed and output on the RD output. The clock recovered from the XFI data (TD) is used as the timing source for the RD output.
PAGE 34
Si5040 9. Pattern Generation and Checking The Si5040 includes a programmable pattern generator and checker function in both the receiver and transmitter signal paths. The Si5040 can generate and check PRBS7, PRBS31, or a 64-bit, user-defined pattern programmed in the tpSel register (receiver Register 29, transmitter Register 157). Notes: 1.
PAGE 35
Si5040 10. Serial Microcontroller Interface Device control and status monitoring is supported with a selectable I2C or SPI-like interface. SPSEL (Pin 9) controls which of the two serial formats is selected. 10.1. I2C Interface When configured in I2C control mode (pin SPSEL tied low), the control interface to the Si5040 is a 2-wire bus for bidirectional communication. The bus consists of a bidirectional serial data line (SD) and a serial clock input (SCK).
PAGE 36
Si5040 10.2. SPI-Like Interface When configured in SPI-like control mode (pin SPSEL tied high), the control interface to the Si5040 is a 3-wire interface modeled close to commonly-available microcontrollers and bidirectional serial peripheral devices. The interface consists of a clock input (SCK), slave select input (SS), and serial data input/output (SD). The SD pin may be configured as a CMOS output or as an open drain output using Register 2, bit 4.
PAGE 37
Si5040 11. Interrupt Functionality Alarm Status bits (Register 9/137) are sampled by a 10 MHz clock to create the Interrupt Status bits (Register 5/133). If the Interrupt Enable bit (Register 2, bit 5) is a zero, all the Interrupt status bits are forced to zero. The Alarm Status bits are always active regardless of the state of the Interrupt Enable bit and the Interrupt Mask bits. The Interrupt Mask bits (Register 4/132) masks the Alarms Status bits from affecting the corresponding Interrupt Status bit.
PAGE 38
Si5040 RX_REFLOS Interrupt Status (sticky) bit (Register 5, bit 6) RX_REFLOS Alarm status bit (Register 9, bit 6) Q D CK RX_REFLOS Interrupt mask bit (Register 4, bit 6) C 10 MHz Clock Clear RX_LOS Alarm status bit (Register 9, bit 5) Interrupt Enable (Register 2, bit 5) Q D CK C 10 MHz Clock Write-to-Clear Clear RX_LOL Alarm status bit (Register 9, bit 4) RX_LOL Interrupt Status (sticky) bit (Register 5, bit 4) Q RX_LOL Interrupt mask bit (Register 4, bit 4) C 10 MHz Clock Clear RX_
PAGE 39
Si5040 12. Programmable Power Down Options The RX and TX paths can be powered down independently by programming RxPdn = 1 at Register 3, Bit 0 (Default = 0) or TxPdn = 1 at Register 131, Bit 0 (Default = 0), respectively. As long as both paths are not powered down, all registers are still accessible.
PAGE 40
Si5040 13. Si5040 Register Summary Any reserved bits listed in the table below or reserved registers (23, 54–55, 58–76, 78–83, 86–97, 99–105, 110– 130, 140–144, 148–151, 182–183, 185–204, 206–225, and 227–255) must not be written to a non-default value. All reserved bits have the default values shown below.
PAGE 41
Si5040 Reg Name Default Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 30 RxtpChkConfig 2h Reserved Reserved Reserved Reserved Reserved tpSyncMask 31 RxtpArbGenPtn AAh RxtpArbGenPtn[7:0] 32 RxtpArbGenPtn AAh RxtpArbGenPtn[15:8] 33 RxtpArbGenPtn AAh RXtpArbGenPtn[23:16] 34 RxtpArbGenPtn AAh RxtpArbGenPtn[31:24] 35 RxtpArbGenPtn AAh RxtpArbGenPtn[39:32] 36 RxtpArbGenPtn AAh RxtpArbGenPtn[47:40] 37 RxtpArbGenPtn AAh RxtpArbGenPtn[55:48] 38 RxtpArbGenPtn AAh RxtpArbGenPtn[6
PAGE 42
Si5040 Reg Name Default Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 132 TxintMask 0h Reserved refLOS LOS LOL fifoErr tpErrAlarm tpSyncLos sqmAlarm 133 TxintStatus (Sticky Bits) 0h Reserved refLOS LOS LOL fifoErr tpErrAlarm tpSyncLos sqmAlarm 134 TxCmuConfig 40h 135 TxConfig 94h Reserved Reserved Reserved CDRLTDATA uselolMode 136 TxCalConfig 0h Reserved Reserved Reserved Reserved hardRecal 137 TxAlarmStatus 0h Reserved refLOS LOS LOL fifoErr 138
PAGE 43
Si5040 Reg Name Default Bit 7 Bit 6 174 TxtpArbChkPtn AAh TxtpArbChkPtn[63:56] 175 TxtpTargetErr FFh TxtpTargetErr[7:0] 176 TxtpChkErrCnt N/A TxtpChkErrCnt[7:0] 177 TxtpChkErrCnt N/A TxtpChkErrCnt[15:8] 178 TxtpChkErrCnt N/A TxtpChkErrCnt[23:16] 179 TxtpChkErrCnt N/A TxtpChkErrCnt[31:24] 180 TxtpChkErrCnt N/A TxtpChkErrCnt[39:32] 181 TxtpChkErr N/A TxtpChkErr[7:0] 184 OutputLevel F5h 205 TxPDGainAcq 8Dh 226 TxLoopFAcq 1Eh HsPowerCtl[1:0] Bit 5 Reserved TxPDGa
PAGE 44
Si5040 Register 0. Part Identifier Bit D7 D6 D5 D4 D3 Name Identifier[7:0] Type R D2 D1 D0 Reset settings = 0100 0000 Bit Name 7:0 Identifier[7:0] Function Second and least significant digit of the device part number (40). Register 1. Part Identifier Bit D7 D6 D5 D4 D3 D1 Name Revision[3:0] Identifier[3:0] Type R R Reset settings = 0011 0000 Bit Name 7:4 Revision[3:0] Die revision (Revision D = 3 decimal). 3:0 Identifier[3:0] Third digit of the device number (0).
PAGE 45
Si5040 Register 2. ChipConfig1 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name losOpenDrain intOpenDrain intEnable spiOpenDrain Reserved lineside Loopback XFI Loopback refClkFreq Type R/W R/W R/W R/W R/W R/W R/W R/W Reset settings = 0101 1000 Bit Name Function 7 losOpenDrain RX LOS Output Select. 0 = CMOS output. 1 = Open Drain. 6 intOpenDrain Interrupt Pin Drive Select. 0 = CMOS output. 1 = Open Drain. 5 intEnable 4 spiOpenDrain 3 Reserved Do not change.
PAGE 46
Si5040 Register 3. RxChipConfig2 Bit D7 D6 D5 D4 D3 D2 D1 Name Type D0 RxPdn R R R R R R R R/W Reset settings = 0000 0000 Bit Name 7:1 Reserved 0 RxPdn 46 Function Read returns zero. Receiver Power Down. 0 = Normal operation. 1 = Receiver powered down. A hard recal must be performed to calibrate all circuits (RX hardRecal at Register 8, Bit 3) when the receiver is returned to normal operation after a power down. Rev. 1.
PAGE 47
Si5040 Register 4. RxintMask Bit D7 Name Type R D6 D5 D4 D3 refLOS LOS LOL fifoErr R/W R/W R/W R/W D2 D1 tpErrAlarm tpSyncLos R/W R/W D0 sqmAlarm R/W Reset settings = 0000 0000 Bit Name Function 7 Reserved 6 refLOS Reference Clock LOS Interrupt. 0 = Unmasked. Reference clock LOS generates an alarm on the Interrupt output pin (pin 16) if interrupts are enabled. (intEnable = 1) 1 = refLOS alarm is ignored. 5 LOS Loss of Signal Interrupt. 0 = Unmasked.
PAGE 48
Si5040 Register 5. RxintStatus (Sticky Bits) Bit D7 Name Type R D6 D5 D4 D3 refLOS LOS LOL fifoErr R/W R/W R/W R/W D2 D1 tpErrAlarm tpSyncLos R/W R/W D0 sqmAlarm R/W Reset settings = 0000 0000 Bit Name 7 Reserved 6 refLOS Reference Clock LOS Interrupt. A latched version of the refLOS alarm status bit. An interrupt is generated if interrupts are enabled (intEnable = 1) and if not masked by the corresponding interrupt mask bit.
PAGE 49
Si5040 Register 6. RxCmuConfig Bit D7 D6 D5 D4 D3 D2 D1 Name cmuBandwidth[3:0] Reserved Reserved Type R/W R R/W D0 Reset settings = 0100 0000 Bit 7:4 Name Function cmuBandwidth[3:0] RxCMU Jitter Transfer Bandwidth. 0000 = Not supported 0001 = Not supported 0010 = Not supported 0011 = Not supported 0100 = 380 kHz Default 0101 = Not supported 0110 = Not supported 3 Reserved Read returns zero. 2:0 Reserved Do not change; must only write 000 to these bits. Rev. 1.
PAGE 50
Si5040 Register 7. RxConfig Bit D7 Name Type D6 D5 D4 D3 D2 D1 D0 lolOnLOS ltrOnLOS CDRLTDATA uselolMode lolMode ltr rxRefclkEn R/W R/W R/W R/W R/W R/W R/W R Reset settings = 0001 0101 Bit Name 7 Reserved Read returns zero. 6 lolOnLOS Loss of Lock on Loss of Signal. 0 = Normal LOL operation. 1 = Assert loss of lock on a loss of signal condition. 5 ltrOnLOS Lock to Reference on Loss of Signal. 0 = Normal LTR operation.
PAGE 51
Si5040 Register 8. RxCalConfig Bit D7 D6 D5 D4 Name Type D3 hardRecal R R R R R/W D2 D1 VCOCAL[1:0] R/W R/W D0 swReset R/W Reset settings = 0000 0000 Bit Name Function 7:4 Reserved Read returns zero. 3 hardRecal Force Recalibarions. 0 = Normal operation 1 = Initiate all calibrations of internal circuits and do not reset all RX registers. Bit is cleared upon completion of calibrations. 2:1 VCOCAL[1:0] Receive VCO Calibration Modes.
PAGE 52
Si5040 Register 9. RxAlarmStatus Bit D7 Name Type R D6 D5 D4 D3 refLOS LOS LOL fifoErr R R R R D2 D1 tpErrAlarm tpSyncLos R D0 sqmAlarm R R Reset settings = 0000 0000 Bit Name 7 Reserved 6 refLOS 5 LOS Function Read returns zero. Reference Clock LOS Alarm. Loss of signal on the reference clock input, based on a coarse deviation in frequency. Loss of Signal Alarm. Loss of signal on the receiver input.
PAGE 53
Si5040 Register 10. RxLosCtrl Bit D7 D6 D5 D4 Name Type R R R R D3 D2 D1 D0 sqmLosEn dLosEn[1:0] aLosEn R/W R/W R/W Reset settings = 0000 0001 Bit Name Function 7:4 Reserved Read returns zero. 3 sqmLosEn Signal Quality Monitor LOS Enable. 0 = Disabled. 1 = Signal Quality Monitor alarm causes an LOS alarm. 2:1 dLosEn[1:0] 0 aLosEn Digital LOS Enable Mode. 00 = Disabled. 01 = Digital LOS alarm is based on the consecutive number of zeros programmed in Register 17.
PAGE 54
Si5040 Register 11. RxLosStatus Bit D7 D6 D5 Name Type R R R D4 D3 D2 D1 D0 sqmLOS dLOSlastTrigger dLOS aLOS LOS R R R R R Reset settings = 0000 0000 Bit Name 7:5 Reserved 4 sqmLOS Function Read returns zero. Signal Quality Monitor LOS. When the internal signal quality monitor (Reg25) is less than the threshold in registers 26 and 27, this bit will be high. If a LOL (Reg9[4]) is high, this bit is forced to a 0. dLOSlastTrigger Digital Loss of Signal Last Trigger.
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Si5040 Register 13. aLosThresh2 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name aLosHyst[3:0] Reserved aLosThresh[9:8] Type R/W R R/W Reset settings = 0111 0000 Bit Name 7:4 aLosHyst[3:0] 3:2 Reserved 1:0 aLosThresh[9:8] Function Analog Loss of Signal Hysteresis. Analog LOS deassert value = (aLosHyst + 16)/16 * aLosThresh in mVppd. Read returns zero. Analog Loss of Signal Threshold. Upper two bits of the analog threshold value in mVppd. Notes: 1. Maximum analog LOS threshold is 400 mVppd. 2.
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Si5040 Register 16. peakDet Bit D7 D6 D5 D4 D3 D2 Name D1 D0 peakDet[1:0] Type R R Reset settings = 0000 0000 Bit Name 7:2 Reserved 1:0 peakDet[9:8] Function Read returns zero. Peak Detector Signal Amplitude. Most significant two bits of the receiver peak detector signal amplitude in mV. This register should be read after reading Register 15. Note: Combined with Register 15, 00 0000 0000 = 0 mV 11 1111 1111 = 1022 mV Register 17.
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Si5040 Register 18. RxdLosClearThresh Bit D7 D6 D5 D4 D3 Name RxdLosClearThresh[7:0] Type R/W D2 D1 D0 Reset settings = 0110 0000 Bit 7:0 Name Function RxdLosClearThresh[7:0] Receiver Digital Loss of Signal Clear Threshold. Clear threshold that releases a digital LOS event. The number of consecutive 1024 bit fields with at least one transition that are required to clear dLos is calculated as RxdLos clearthresh x 16 + 1. See Figure 11 on page 21. Register 20.
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Si5040 Register 21. sliceLvl Bit D7 D6 D5 D4 D3 Name sliceLvl[7:0] Type R/W D2 D1 D0 Reset settings = 0000 0000 Bit Name 7:0 sliceLvl[7:0] Function Slice Level. Least significant byte of slice level setting. 2's compliment signed value.
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Si5040 Register 24. RxphaseAdjust Bit D7 D6 D5 D4 Name Type D3 D2 D1 D0 RxphaseAdjust[6:0] R R/W Reset settings = 0000 0000 Bit Name 7 Reserved 6:0 Function Read returns zero. RxphaseAdjust[6:0] Receiver Phase Adjust. Programmable range will cover at least –12 to 12 ps. The transfer function from Register 24 to the actual picoseconds of phase shift is highly variable. Value is signed, in 2s complement format: 100 0001 < –12 ps 011 1111 > 12 ps Register 25.
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Si5040 Register 26. RxSqmConfig Bit D7 D6 D5 D4 Name RxSqmThresh[5:0] Type R/W D3 D2 D1 D0 R/W R/W D1 D0 Reset settings = 0010 1001 Bit 7:2 Name Function RxSqmThresh[5:0] Receiver Signal Quality Monitor Threshold. Threshold used to assert SQM LOS alarm. 00 0000 = 0 (decimal) 11 1111 = 63 (decimal) Note: Default = 10 (decimal) 1 Reserved Do not change; must only write 0 to this bit. 0 Reserved Do not change; must only write 1 to this bit. Register 27.
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Si5040 Register 28. RxdPathConfig Bit D7 Name Type D6 dinvert R R/W D5 D4 D3 clkOnLOS SquelchO- SquelchOnRxLOL nRxLOS R/W R/W D2 D1 D0 Squelch FIFOAuto Reset FIFOReset R/W R/W R/W R/W Reset settings = 0000 0010 Bit Name 7 Reserved 6 dinvert 5 clkOnLOS Function Read returns zero. Data Invert. 0 = Normal operation. 1 = RD+ and RD– outputs (pins 19, 18) inverted. Clock Output on Receive Loss of Signal. 0 = Normal operation.
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Si5040 Register 29. RxtpSel Bit D7 D6 D5 D4 D3 D2 D1 Name tpChkInvert tpChkSel[2:0] tpGenInvert tpGenSel[2:0] Type R/W R/W R/W R/W D0 Reset settings = 0000 0000 Bit Name 7 tpChkInvert 6:4 tpChkSel[2:0] 3 tpGenInvert 2:0 tpGenSel[2:0] Function Test Pattern Checker Data Invert. 0 = Normal operation. 1 = Invert data applied to test pattern checker. Test Pattern Checker Mode Select. 000 = Pattern checker disabled. 001 = Check for PRBS7 pattern. 010 = Check for PRBS31 pattern.
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Si5040 Register 30. RxtpChkConfig Bit D7 D6 D5 D4 D3 D2 Name Type D1 D0 tpSyncMask tpTimeBase[1:0] R/W R/W R Reset settings = 0000 0010 Bit Name 7:3 2 Reserved tpSyncMask 1:0 Function Read returns zero. Test Pattern Checker Sync Mask. 0 = Normal operation. 1 = After synchronization has been achieved a loss of sync will not be reported and the pattern checker will not be reset. tpTimeBase[1:0] Test Pattern Checker Timebase.
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Si5040 Register 32. RxtpArbGenPtn Bit D15 D14 D13 D12 D11 Name RxtpArbGenPtn[15:8] Type R/W D10 D9 D8 Reset settings = 1010 1010 Bit 7:0 Name Function RxtpArbGenPtn[15:8] Receiver Test Pattern Generator User Defined Pattern. Note: Bit 0 in Register 31 is the LSB of the 64-bit user-defined pattern, and Bit 7 in Register 38 is the MSB. The transmit sequence is from LSB to MSB. Register 33.
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Si5040 Register 35. RxtpArbGenPtn Bit D39 D38 D37 D36 D35 Name RxtpArbGenPtn[39:32] Type R/W D34 D33 D32 Reset settings = 1010 1010 Bit 7:0 Name Function RxtpArbGenPtn[39:32] Receiver Test Pattern Generator User Defined Pattern. Note: Bit 0 in Register 31 is the LSB of the 64-bit user-defined pattern, and Bit 7 in Register 38 is the MSB. The transmit sequence is from LSB to MSB. Register 36.
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Si5040 Register 38. RxtpArbGenPtn Bit D63 D62 D61 D60 D59 Name RxtpArbGenPtn[63:56] Type R/W D58 D57 D56 Reset settings = 1010 1010 Bit 7:0 Name Function RxtpArbGenPtn[63:56] Receiver Test Pattern Generator User Defined Pattern. Note: Bit 0 in Register 31 is the LSB of the 64-bit user-defined pattern, and Bit 7 in Register 38 is the MSB. The transmit sequence is from LSB to MSB. Register 39.
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Si5040 Register 41. RxtpArbChkPtn Bit D23 D22 D21 D20 D19 Name RxtpArbChkPtn[23:16] Type R/W D18 D17 D16 Reset settings = 1010 1010 Bit 7:0 Name Function RxtpArbChkPtn[23:16] Receiver Test Pattern Checker User Defined Pattern. Note: Bit 0 in Register 39 is the LSB of the received 64-bit user-defined pattern, and Bit 7 in Register 46 is the MSB. The receive sequence is from LSB to MSB. Register 42.
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Si5040 Register 44. RxtpArbChkPtn Bit D47 D46 D45 D44 D43 Name RxtpArbChkPtn[47:40] Type R/W D42 D41 D40 Reset settings = 1010 1010 Bit 7:0 Name Function RxtpArbChkPtn[47:40] Receiver Test Pattern Checker User Defined Pattern. Note: Bit 0 in Register 39 is the LSB of the received 64-bit user-defined pattern, and Bit 7 in Register 46 is the MSB. The receive sequence is from LSB to MSB. Register 45.
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Si5040 Register 47. RxtpTargetErr Bit D7 D6 D5 D4 D3 Name RxtpTargetErr[7:0] Type R/W D2 D1 D0 Reset settings = 1111 1111 Bit Name 7:0 Function RxtpTargetErr[7:0] Receiver Test Pattern Checker Target Error Count. If the value in the RxtpChkErrCnt register (register 53) exceeds this target error count, an interrupt will be generated. The value is represented as an 8-bit floating point number.
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Si5040 Register 49. RxtpChkErrCnt (40-bit Register) Bit D15 D14 D13 D12 D11 Name RxtpChkErrCnt[15:8] Type R D10 D9 D8 Reset settings = undefined Bit 7:0 Name Function RxtpChkErrCnt[15:8] Receiver Test Pattern Checker Error Count. When using a defined timebase, this register holds the error count from the last completed timebase. In the continuous timebase setting, the register holds the current running error count. Reading the least significant byte latches the upper bytes. Register 50.
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Si5040 Register 52. RxtpChkErrCnt (MSB of a 40-bit Register) Bit D39 D38 D37 D36 D35 Name RxtpChkErrCnt[39:32] Type R D34 D33 D32 Reset settings = undefined Bit Name 7:0 Function RxtpChkErrCnt[39:32] Receiver Test Pattern Checker Error Count. When using a defined timebase, this register holds the error count from the last completed timebase. In the continuous timebase setting, the register holds the current running error count. Reading the least significant byte latches the upper bytes.
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Si5040 Register 56. OutputLevel Bit D7 D6 Name Reserved Type R/W D5 D4 D3 D2 D1 D0 outLevel[2:0] Reserved R/W Reset settings = 1111 0101 Bit Name Function 7:6 Reserved Do not change; must only write 11 to these bits. 5:3 Reserved These bits are not user defined, and writes to these bits are ignored. 2:0 outLevel[2:0] RD output drive level. 000 = 100 mVppd 001 = 200 mVppd 010 = 300 mVppd 011 = 400 mVppd 100 = 500 mVppd 101 = 600 mVppd 110 = 700 mVppd 111 = 800 mVppd Register 77.
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Si5040 Register 84. RxEqConfig1 Bit D7 D6 D5 D4 D3 D2 Name RxEqGain Reserved Type R/W R/W D1 D0 Reset settings = 1010 0001 Bit Name Function 7:5 RxEqGain Low-Frequency Gain in the Receiver Equalizer Frequency Response. 000 0 dB (max gain) 001 –2 dB 010 –2 dB (same as 001 setting) 011 –3 dB 100 –4 dB 101 –5 dB 110 –6 dB 111 –7 dB (min gain) 4:0 Reserved Do not change; must only write 00001 to these bits. Register 85.
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Si5040 Register 98. RxLoopFAcq Bit D7 D6 D5 D4 D3 Name RxLoopFAcqCtl RxLoopFAcq[6:0] Type R/W R/W D2 D1 D0 Reset settings = 0001 1110 Bit Name 7 RxLoopFAcqCtl 6:0 RxLoopFAcq[6:0] Function RX Acquistion Loop Filter Override. 1 = Use value written in Bit [6:0]. Set to 1 only when RX LOL is asserted. 0 = Use internally generated value. Set to 0 when RX LOL is deasserted. RX Loop Filter Setting for Acquisition. RX Loop filter override setting to be used during acquisiton.
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Si5040 Register 107. sqmLOLThresh Bit D7 D6 D5 D4 D3 Name sqmLOLThresh[0] Reserved Type R/W R/W D2 D1 D0 Reset settings = 0000 0000 Bit 7 Name Function sqmLOLThresh[0] SQM LOL Threshold. Least significant bit of 14 bit SQM LOL Threshold setting; value is unsigned integer value. RxLOL is asserted when jitter measure exceeds value in sqmLOLThresh[13:0] and is deasserted when jitter measure is below the threshold. Refer to "5.8.1. SQM LOL" on page 24 for more information about this register.
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Si5040 Register 109. sqmLOLThresh Bit D7 D6 D5 D4 D3 D2 D1 Name Reserved sqmLOLThresh[13:9] Type R/W R/W D0 Reset settings = 0000 0000 Bit Name 7:5 Reserved 4:0 Function Reserved. Should be written to 101b. sqmLOLThresh[13:9] SQM LOL Threshold. Bit [13:9] of sqmLOL Threshold setting; value is unsigned integer value. RxLOL is asserted when jitter measure exceeds value in sqmLOLThresh[13:0] and is deasserted when jitter measure is below the threshold. Refer to Section 5.8.
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Si5040 Register 132. TxintMask Bit D7 Name Type R D6 D5 D4 D3 refLOS LOS LOL fifoErr R/W R/W R/W R/W D2 D1 tpErrAlarm tpSyncLos R/W R/W D0 sqmAlarm R/W Reset settings = 0000 0000 Bit Name Function 7 Reserved 6 refLOS Reference Clock LOS Interrupt. 0 = Unmasked. Reference clock LOS generates an alarm on the Interrupt output pin (pin 12) if interrupts are enabled. (intEnable = 1). 1 = refLOS alarm is ignored. 5 LOS Loss of Signal Interrupt. 0 = Unmasked.
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Si5040 Register 133. TxintStatus (Sticky Bits) Bit D7 Name Type R D6 D5 D4 D3 refLOS LOS LOL fifoErr R/W R/W R/W R/W D2 D1 tpErrAlarm tpSyncLos R/W R/W D0 sqmAlarm R/W Reset settings = 0000 0000 Bit Name 7 Reserved 6 refLOS Reference Clock LOS Interrupt. A latched version of the refLOS alarm status bit. An interrupt is generated if interrupts are enabled (intEnable = 1) and if not masked by the corresponding interrupt mask bit.
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Si5040 Register 134. TxCmuConfig Bit D7 D6 D5 Name cmuBandwidth[3:0] Type R/W D4 D3 D2 D1 D0 cmuMode[2:0] R R/W Reset settings = 0100 0000 Bit 7:4 Name Function cmuBandwidth[3:0] TxCMU Jitter Transfer Bandwidth. 0000 = 180 Hz Valid for CMU modes 2 and 6. 0001 = 1.37 kHz Valid for CMU modes 2 and 6. 0010 Not supported. 0011 Not supported. 0100 = 380 kHz Valid for CMU modes 0 and 1 only. 0101 Not supported. 0110 Not supported.
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Si5040 Register 135. TxConfig Bit D7 D6 D5 Name Type D4 D3 D2 D1 CDRLTDATA uselolMode lolMode ltr R/W D0 R Reset settings = 1001 0100 Bit Name 7:5 Reserved 4 CDRLTDATA 3 uselolMode Loss of Lock Mode Overwrite. 0 = Auto select LOL mode is based upon the tx CMU mode. The selected LOL mode can be read from the LOL mode bit 2. 1 = LOL is based on lolMode bit2. 2 lolMode Loss of Lock Mode (This bit is only used if bit3 = 1).
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Si5040 Register 136. TxCalConfig Bit D7 D6 D5 D4 Name Type D3 hardRecal R R R R R/W D2 D1 VCOCAL[1:0] R/W R/W D0 swReset R/W Reset settings = 0000 0000 Bit Name Function 7:4 Reserved Read returns zero. 3 hardRecal Force Recalibrations. 0 = Normal operation 1 = Initiate all calibrations of internal circuits and do not reset all TX registers. Bit is cleared upon completion of calibrations. 2:1 VCOCAL[1:0] Transmit VCO Calibration Modes.
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Si5040 Register 137. TxAlarmStatus Bit D7 Name Type R D6 D5 D4 D3 refLOS LOS LOL fifoErr R R R R D2 D1 tpErrAlarm tpSyncLos R D0 sqmAlarm R R Reset settings = 0000 0000 Bit Name 7 Reserved 6 refLOS 5 LOS Loss of Signal Alarm. Loss of signal on the transmitter input. (TD) 4 LOL Loss of Lock Alarm. The transmitter PLL has lost lock with the transmitter input signal. (TD) 3 fifoErr 2 tpErrAlarm Test Pattern Generator/Checker Alarm.
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Si5040 Register 138. TxLosCtrl Bit D7 D6 D5 D4 D3 Name Type R D2 D1 sqmLosEn dLosEn[1:0] R/W R/W D0 R Reset settings = 0000 1110 Bit Name Function 7:4 Reserved Read returns zero. 3 sqmLosEn Signal Quality Monitor LOS Enable. 0 = Disabled. 1 = Signal Quality Monitor alarm causes an LOS alarm. 2:1 dLosEn[1:0] 0 Reserved Digital LOS Enable Mode. 00 = Disabled. 01 = Digital LOS alarm is based on the consecutive number of zeros programmed in Register 145.
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Si5040 Register 145. TxdLosAssertThresh Bit D7 D6 D5 D4 D3 Name TxdLosAssertThresh[7:0] Type R/W D2 D1 D0 Reset settings = 0000 0000 Bit 7:0 Name Function TxdLosAssertThresh Transmitter Digital Loss of Signal Assert Threshold. The number of consecutive identical digits before digital LOS is asserted. Assert threshold in bits = (TxdLosAssertThresh x 5 + 2) x 1024. See Figure 10 on page 20. Register 146.
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Si5040 Register 152. TxphaseAdjust Bit D7 D6 D5 D4 Name Type D3 D2 D1 D0 TxphaseAdjust[6:0] R R/W Reset settings = 0000 0000 Bit Name 7 Reserved 6:0 Function Read returns zero. TxphaseAdjust[6:0] Transmitter Phase Adjust. Programmable range will cover at least –12 to 12 ps. The transfer function from Register # to actual ps of phase shift is highly variable. Value is signed, in 2s complement format: 100 0001 < –12 ps 011 1111 > 12 ps Register 153.
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Si5040 Register 154. TxSqmConfig Bit D7 D6 D5 D4 Name TxSqmThresh[5:0] Type R/W D3 D2 D1 D0 R/W R/W D1 D0 Reset settings = 0000 0101 Bit 7:2 Name Function TxSqmThresh[5:0] Transmitter Signal Quality Monitor Threshold. Threshold used to assert SQM LOS alarm. 00 0000 = 0 (decimal) 11 1111 = 63 (decimal) Note: Default = 1 (decimal) 1 Reserved Do not change; must only write a 0 to this bit. 0 Reserved Do not change; must only write a 1 to this bit. Register 155.
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Si5040 Register 156. TxdPathConfig Bit D7 Name Type D6 D5 dinvert clkOnLOS R/W R/W R D4 D3 D2 SquelchOnTxLOL SquelchOnTxLOS Squelch R/W R/W D1 D0 FIFOAutoReset FIFOReset R/W R/W R/W Reset settings = 0000 0010 Bit Name 7 Reserved 6 dinvert 5 clkOnLOS Function Read returns zero. Data Invert. 0 = Normal operation. 1 = TXDOUT+ and TXDOUT– outputs (pins 30, 29) are inverted. Clock Output on Transmitter Loss of Signal. 0 = Normal operation.
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Si5040 Register 157. TxtpSel Bit D7 D6 D5 D4 D3 D2 D1 Name tpChkInvert tpChkSel[2:0] tpGenInvert tpGenSel[2:0] Type R/W R/W R/W R/W D0 Reset settings = 0000 0000 Bit Name 7 tpChkInvert 6:4 tpChkSel[2:0] 3 tpGenInvert 2:0 tpGenSel[2:0] Function Test Pattern Checker Data Invert. 0 = normal operation. 1 = invert data applied to test pattern checker. Test Pattern Checker Mode Select. 000 = pattern checker disabled. 001 = check for PRBS7 pattern. 010 = check for PRBS31 pattern.
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Si5040 Register 158. TxtpChkConfig Bit D7 D6 D5 D4 D3 Name Type D2 D1 D0 tpSyncMask tpTimeBase[1:0] R/W R/W R Reset settings = 0000 0010 Bit Name 7:3 Reserved 2 tpSyncMask 1:0 Function Read returns zero. Test Pattern Checker Sync Mask. 0 = Report loss of sync, followed by reset. 1 = After synchronization has been achieved a loss of sync will not be reported and the pattern checker will not be reset. tpTimeBase[1:0] Test Pattern Checker Timebase.
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Si5040 Register 160. TxtpArbGenPtn Bit D15 D14 D13 D12 D11 Name TxtpArbGenPtn[15:8] Type R/W D10 D9 D8 Reset settings = 1010 1010 Bit 7:0 Name Function TxtpArbGenPtn[15:8] Transmitter Test Pattern Generator User Defined Pattern. Note: Bit 0 in Register 159 is the LSB of the 64-bit user-defined pattern, and Bit 7 in Register 166 is the MSB. The transmit sequence is from LSB to MSB. Register 161.
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Si5040 Register 163. TxtpArbGenPtn Bit D39 D38 D37 D36 D35 Name TxtpArbGenPtn[39:32] Type R/W D34 D33 D32 Reset settings = 1010 1010 Bit 7:0 Name Function TxtpArbGenPtn[39:32] Transmitter Test Pattern Generator User Defined Pattern. Note: Bit 0 in Register 159 is the LSB of the 64-bit user-defined pattern, and Bit 7 in Register 166 is the MSB. The transmit sequence is from LSB to MSB. Register 164.
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Si5040 Register 166. TxtpArbGenPtn Bit D63 D62 D61 D60 D59 Name TxtpArbGenPtn[63:56] Type R/W D58 D57 D56 Reset settings = 1010 1010 Bit 7:0 Name Function TxtpArbGenPtn[63:56] Transmitter Test Pattern Generator User Defined Pattern. Note: Bit 0 in Register 159 is the LSB of the 64-bit user-defined pattern, and Bit 7 in Register 166 is the MSB. The transmit sequence is from LSB to MSB. Register 167.
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Si5040 Register 169. TxtpArbChkPtn Bit D23 D22 D21 D20 D19 Name TxtpArbChkPtn[23:16] Type R/W D18 D17 D16 Reset settings = 1010 1010 Bit 7:0 Name Function TxtpArbChkPtn[23:16] Transmitter Test Pattern Checker User Defined Pattern. Note: Bit 0 in Register 167 is the LSB of the received 64-bit user-defined pattern, and Bit 7 in Register 174 is the MSB. The receive sequence is from LSB to MSB. Register 170.
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Si5040 Register 172. TxtpArbChkPtn Bit D47 D46 D45 D44 D43 Name TxtpArbChkPtn[47:40] Type R/W D42 D41 D40 Reset settings = 1010 1010 Bit 7:0 Name Function TxtpArbChkPtn[47:40] Transmitter Test Pattern Checker User Defined Pattern. Note: Bit 0 in Register 167 is the LSB of the received 64-bit user-defined pattern, and Bit 7 in Register 174 is the MSB. The receive sequence is from LSB to MSB. Register 173.
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Si5040 Register 175. TxtpTargetErr Bit D7 D6 D5 D4 D3 Name TxtpTargetErr[7:0] Type R/W D2 D1 D0 Reset settings = 1111 1111 Bit Name 7:0 TxtpTargetErr[7:0] Function Transmitter Test Pattern Checker Target Error Count. If the value in the TxtpChkErrCnt register (register 181) exceeds this target error count, an interrupt will be generated. The value is represented as an 8-bit floating point number.
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Si5040 Register 177. TxtpChkErrCnt (40-bit Register) Bit D15 D14 D13 D12 D11 Name TxtpChkErrCnt[15:8] Type R D10 D9 D8 Reset settings = undefined Bit 7:0 Name Function TxtpChkErrCnt[15:8] Transmitter Test Pattern Checker Error Count. When using a defined timebase, this register holds the error count from the last completed timebase. In the continuous timebase setting, the register holds the current running error count. Reading the least significant byte latches the upper bytes.
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Si5040 Register 180. TxtpChkErrCnt (MSB of a 40-bit Register) Bit D39 D38 D37 D36 D35 Name TxtpChkErrCnt[39:32] Type R D34 D33 D32 Reset settings = undefined Bit 7:0 Name Function TxtpChkErrCnt[39:32] Transmitter Test Pattern Checker Error Count. When using a defined timebase, this register holds the error count from the last completed timebase. In the continuous timebase setting, the register holds the current running error count. Reading the least significant byte latches the upper bytes.
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Si5040 Register 184. OutputLevel Bit D7 D6 D5 D4 D3 D2 D1 Name HsPowerCtl[1:0] Reserved outLevel[2:0] Type R/W R/W R/W Reset settings = 1111 0101 Bit Name 7:6 Reserved Do not change; must only write 11 to these bits. 5:3 Reserved These bits are not user defined, and writes to these bits are ignored. 2:0 outLevel[2:0] 98 Function Output Level. TXDOUT output drive level. 000 = 100 mVppd. 001 = 200 mVppd. 010 = 300 mVppd. 011 = 400 mVppd. 100 = 500 mVppd. 101 = 600 mVppd.
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Si5040 Register 205. TxPDGainAcq Bit D7 D6 D5 D4 D3 D2 Name TxPDGainAcq[2:0] Reserved Type R/W R/W D1 D0 Reset settings = 1000 1101 Bit Name Function 7:5 TxPDGainAcq[2:0] TX phase detector gain during acquisition. Note that these bits require a one time write of 000b after a power-up or a software reset. 4:0 Reserved Reserved; must only write 01101b to these bits. Register 226.
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Si5040 SD 29 SS 30 GND TXDO UT– 31 V DD GND 32 TXDO UT+ V DD 14. Pin Descriptions: Si5040 28 27 26 25 GND 1 24 RX_LOL 2 23 GND RX_LOS 3 22 TD+ VDDIO 4 21 TD– GND 5 20 GND RXDIN– 6 19 RD+ RXDIN+ 7 18 RD– GND 8 17 GND GND PAD GND PAD GND PAD 12 13 14 15 16 REFCLK+ REFCLK- VDD INTERRUPT NC 11 NC 10 V DD 9 SPSEL GND PAD SCK Figure 24. Si5040 Pin Configuration (Transparent Top View) Table 13.
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Si5040 Table 13. Si5040 Pin Descriptions (Continued) Pin Name Type* Level Description 2 RX_LOL DO LVTTL Receiver Loss of Lock (Active High). This output is asserted when the receiver path is in the lossof-lock state. If enabled in the receiver Interrupt Mask register, this event may cause an interrupt. This pin is reflected as bit 4 in Register 9. The latched version of this pin is in Register 5, bit 4.
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Si5040 Table 13. Si5040 Pin Descriptions (Continued) Pin Name Type* Level Description Power and Ground 1, 5, 8, 17, 20, 23, 28, 31 GND P GND Supply Ground. Connect to system GND. Ensure a very low impedance path for optimal performance. Paddle GND P GND Paddle Ground. Must connect to system GND. Ensure a very low impedance path for optimal performance. 12, 15, 27,32 VDD P 1.8 VDC Supply Voltage. Nominally 1.8 V.
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Si5040 15. Ordering Guide Part Number* Package Lead-Free Temperature Si5040-D-GM 32-lead LGA Yes –40 to 95 °C *Note: Add an “R” at the end of the device number to denote the tape and reel option; 2500 quantity per reel. Rev. 1.
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Si5040 16. Package Outline: Si5040 Figure 25 illustrates the package details for the Si5040. Table 14 lists the values for the dimensions shown in the illustration. Figure 25. 32-Pin Land Grid Array Package (LGA) Table 14. Package Diagram Dimensions Dimension Min Nom Max A 0.75 0.85 0.95 b 0.27 0.30 0.33 c 1.00 1.10 1.20 D 5.00 BSC. e 0.50 BSC. E 5.00 BSC. f 0.735 BSC. g 0.735 BSC. h 2.185 BSC. j 2.185 BSC. aaa 0.10 bbb 0.10 ccc 0.10 ddd 0.10 eee 0.10 Notes: 1.
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Si5040 17. Recommended VDD Power Supply Filtering Because of the internal bypass capacitance and voltage regulators, the external supply bypass requirements for the Si5040 are minimal. 1.8 V 12 .1 µF VDD Si5040 VDD 32 .01 µF .01 µF VDD 15 Note: 1. Place a .01 µF cap very close to each VDD pin (12, 15, 27, 32) and place a single 0.1 µF cap close to the Si5040. 2. No power sequencing is required. Rev. 1.3 .01 µF VDD 27 .
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Si5040 DOCUMENT CHANGE LIST Revision 0.5 to Revision 0.8 68, bit3:0) in Table 3  Removed both Stressed Eye Jitter Tolerance and Sinusoidal Jitter Tolerance from Table 3.  Revision 0.8 to Revision 0.85                       Updated final specification numbers for TBD items. Updated register name in Register 16. Changed aLosThresh[1:0] to aLosThresh[9:8] in Register 13. Jitter Tolerance measurement frequency changed from 400 MHz to 80 MHz.
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Si5040 Revision 0.86 to Revision 1.2       Removed sections 5.8.3 and 6.4.3 since fast acquisition is no longer supported. Clarified operation of Register 7[3:2] in register descriptions and "5.8.1. SQM LOL" on page 24. Updated part number in "15. Ordering Guide" on page 103. Added information on voltage application to VDD and VDDIO in pin descriptions. Removed reference to Mode 7 from Register 134 since Mode 7 does not exist.
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Si5040 CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.