User manual

Tasks and Kits
3-14 ProMaster 2500 User Manual
•
Serial Vector Test
— The 2500 applies test vectors to the device
inputs in parallel. If the PLD design requires certain input pins to
be applied before others, the JEDEC standard states that the test
vectors must be written to enforce that particular order. When this
option has been selected, the 2500 applies the vector inputs starting
with device pin 1 and continuing in numeric order to the last input.
This option will not harm the device and should be used as a
troubleshooting tool when a large number of devices are passing
fuse verify but failing test vectors. It is not enabled by default.
•
DIP/LCC vector translation
— In some instances the test vectors in
the JEDEC file were written for a DIP device but will be used to verify
a PLCC part. When this translation option is selected, the 2500
automatically translates the DIP test vectors during the download
into the correct format to test the PLCC/LCC part.
Data Sumcheck
This optional parameter, when selected, will check the sumcheck at the
end of the file transfer with the sumcheck entered in this Task field. For
additional information on this parameter, see page 3-18.
Creating a Task for a Memory Device
Creating a Task for a memory device requires that you define the same
mandatory fields used in the logic device Task (see page 3-4). Entering
the parameters for these mandatory fields follows the same procedures
that you used for the logic devices. The following mandatory parameters
must be defined before a Memory Task will run.
• Define one or more
Device(s)
•Select
Data Source
•Select
Data File
and
Translation Format
• Select one or more
Process(es)
•Select
< More... >
and
Handling/Labeling Parameters...
(Package
type, Pin 1 Orientation, Print Density, and Text).
Figure 3-10
Memory Device Task