User manual

Tasks and Kits
ProMaster 2500 User Manual 3-13
TaskLink displays the Logic Device Parameters dialog box with these
main options:
•
Verify Options
— Select one option from the three offered.
•
Fuse verify only
— Compares the fuses programmed in the logic
device with the pattern in the 2500’s RAM. No structured test
vectors are applied to the device even if they were downloaded in
the JEDEC data file.
•
Functional test only
— Verifies the programmed device using the
structured test vectors downloaded with the JEDEC data file. The
fuses in the device are not checked. This is useful when the devices
have had their security fuse programmed so that the fuse pattern in
their main array can no longer be read by the programmer. Vectors
written for the device will confirm that the device is functioning
correctly if all vectors pass.
•
Fuse verify
and
functional test
(default)—Verifies the
programmed device by comparing the device fuses against the
fuses in RAM. If the device passes, the test vectors are applied to
the device. If all the fuses verify and the vectors pass, the device is
labeled and placed in the pass output tube.
•
Vector Options
— Select any combination of these three options to
change the way logic test vectors are applied to your device during
the verify cycle. These test vector options may improve the yield of
devices that pass fuse verify but fail test vectors. Certain PLD Tasks
may experience a higher failure rate when test vectors are run. These
failures are usually a combination of conditions in the design (as
defined in the JEDEC file), the internal characteristics of the device,
and the way the 2500 applies vectors. These test vector options affect
the way the 2500 applies the file’s test vectors to the device in an
attempt to improve the number of devices that pass test vectors.
•
Compensated Vectors
— Some PLD designs create combinatorial
latches on registered outputs and may fail test vectors even though
the devices have been programmed correctly. This is most often
due to a combination of factors including the specific PLD design,
the device’s internal hardware characteristics, and the
programming electronics in the 2500. If this parameter has been
disabled and a large number of combinatorial output devices are
failing test vectors, selecting Compensated Vectors may improve
the yield. This parameter is enabled by default in TaskLink.
•
High-speed Drivers
— Some PLD designs, when implemented in
certain high-speed PLDs, will fail test vectors even though the
device programmed correctly and functions correctly in-circuit.
The High-speed Drivers option (which is enabled by default)
applies the vector inputs to the device at a higher speed, using a
higher current drive.
Note: Because this option is enabled by default, be careful how you write your
drivers. If the JEDEC file test vectors have not been written correctly, this
higher current applied to a bi-directional input pin might damage some
devices.