User`s guide

CY7C66013
C
CY7C66113
C
Document #: 38-08024 Rev. *B Page 9 of 61
Logic Block Diagram
Interrupt
Controller
PROM
12-bit
Timer
Reset
Watchdog
Timer
Repeater
Power-On
SCLK
I
2
C
USB
Transceiver
USB
Transceiver
USB
Transceiver
GPIO
PORT 1
GPIO
PORT 0
P0[0]
P0[7]
P1[0]
P1[7]
SDATA
D+[3]
D–[3]
D+[2]
D–[2]
8-bit Bus
External 6-MHz crystal
RAM
USB
SIE
USB
Transceiver
D+[4]
D–[4]
USB
Transceiver
D+[0]
D–[0]
D+[1]
D–[1]
Upstream
USB Port
Downstream USB Ports
GPIO
PORT 3
P3[0]
P3[4]
DAC
PORT
DAC[0]
DAC[7]
High Current
Outputs
CY7C66113C only
256 byte
8 KB
Clock
6 MHz
12-MHz
8-bit
CPU
*I
2
C-compatible interface enabled by firmware through
Power management under firmware
control using GPIO pins
Interface
GPIO
PORT 3
P3[5]
P3[6]
Additional
Outputs
High Current
PLL
12 MHz
48 MHz
Divider
GPIO/
PORT 2
P2[0:1,7]
P2[3]; Data_Ready
P2[4]; STB
P2[5]; OE
P2[6]; CS
P2[2]; Latch_Empty
HAPI
P2[1:0] or P1[1:0]