User`s guide

CY7C66013
C
CY7C66113
C
Document #: 38-08024 Rev. *B Page 61 of 61
Document History Page
Document Title: CY7C66013C, CY7C66113C Full-Speed USB (12 Mbps) Peripheral Controller with Integrated Hub
Document Number: 38-08024
REV. ECN NO.
Issue
Date
Orig. of
Change Description of Change
** 114525 3/27/02 DSG Change from Spec number: 38-00591 to 38-08024
*A 124768 03/20/03 MON Added register bit definitions.
Added default bit state of each register.
Corrected the Schematic (location of the pull-up on D+).
Added register summary.
Removed information on the availability of the part in PDIP package.
Modified Table 20-1 and provided more explanation regarding
locking/unlocking mechanism of the mode register.
Removed any information regarding the speed detect bit in Hub Port Speed
register being set by hardware.
*B 417632 See ECN BHA Updated part number and ordering information.
Added QFN Package Drawing and Design Notes.
Corrected bit names in Figures 9-3, 9-4, 9-5, 9-8, 9-9, 9-10, 10-5, 16-1, 18-1,
18-2, 18-3, 18-6, 18-7, 18-9, 18-10.
Removed Hub Ports Force Low register address 0x52.
Added HAPI to Interrupt Vector Number 11 in Table 16-1.
Corrected bit names in Section 21.0.
Corrected Units in Table 24.0 for R
UUP
, R
UDN
, R
EXT
, and Z
O.
Added DIE diagram and related information.
Added HAPI to GPIO interrupt vector in Table 5-1 and figure 16-3