User`s guide

CY7C66013

CY7C66113

Document #: 38-08024 Rev. *B Page 45 of 61

SETUP:

The SETUP bit of the endpoint 0 mode register is forced HIGH at this time. This bit is forced HIGH by the SIE until the end of the

data phase of a control write transfer. The SETUP bit can not be cleared by firmware during this time.

The affected mode and counter registers of endpoint 0 are locked from any CPU writes once they are updated. These registers

can be unlocked by a CPU read, only if the read operation occurs after the UPDATE. The firmware needs to perform a register

read as a part of the endpoint ISR processing to unlock the effected registers. The locking mechanism on mode and counter

registers ensures that the firmware recognizes the changes that the SIE might have made since the previous IO read of that

UPDATE:

1. Endpoint Mode Register – All the bits are updated (except the SETUP bit of the endpoint 0 mode register).

2. Counter Registers – All bits are updated.

3. Interrupt – If an interrupt is to be generated as a result of the transaction, the interrupt flag for the corresponding endpoint is

set at this time. For details on what conditions are required to generate an endpoint interrupt, refer to Table 20-2.

4. The contents of the updated endpoint 0 mode and counter registers are locked, except the SETUP bit of the endpoint 0 mode