User`s guide

CY7C66013
C
CY7C66113
C
Document #: 38-08024 Rev. *B Page 44 of 61
19.4 USB Non-Control Endpoint Mode Registers
The format of the non-control endpoint mode registers is shown in Figure 19-3.
USB Non-Control Device Endpoint Mode ADDRESSES 0x14, 0x16, 0x44
Bits[3..0]: Mode
These sets the mode which control how the control endpoint responds to traffic. The mode bit encoding is shown in
Table 18-1.
Bit 4: ACK
This bit is set whenever the SIE engages in a transaction to the register’s endpoint that completes with an ACK packet.
Bits[6..5]: Reserved
Must be written zero during register writes.
Bit 7: STALL
If this STALL is set, the SIE stalls an OUT packet if the mode bits are set to ACK-IN, and the SIE stalls an IN packet if the
mode bits are set to ACK-OUT. For all other modes, the STALL bit must be a LOW.
19.5 USB Endpoint Counter Registers
There are five Endpoint Counter registers, with identical formats for both control and non-control endpoints. These registers
contain byte count information for USB transactions, as well as bits for data packet status. The format of these registers is shown
in Figure 19-4.
USB Endpoint Counter ADDRESSES 0x11, 0x13, 0x15, 0x41, 0x43
Bits[5..0]: Byte Count
These counter bits indicate the number of data bytes in a transaction. For IN transactions, firmware loads the count with
the number of bytes to be transmitted to the host from the endpoint FIFO. Valid values are 0 to 32, inclusive. For OUT or
SETUP transactions, the count is updated by hardware to the number of data bytes received, plus two for the CRC bytes.
Valid values are 2 to 34, inclusive.
Bit 6: Data Valid
This bit is set on receiving a proper CRC when the endpoint FIFO buffer is loaded with data during transactions. This bit is
used OUT and SETUP tokens only. If the CRC is not correct, the endpoint interrupt occurs, but Data Valid is cleared to a
zero.
Bit 7: Data 0/1 Toggle
This bit selects the DATA packet’s toggle state: 0 for DATA0, 1 for DATA1. For IN transactions, firmware must set this bit to
the desired state. For OUT or SETUP transactions, the hardware sets this bit to the state of the received Data Toggle bit.
Whenever the count updates from a SETUP or OUT transaction on endpoint 0, the counter register locks and cannot be written
by the CPU. Reading the register unlocks it. This prevents firmware from overwriting a status update on incoming SETUP or OUT
transactions before firmware has a chance to read the data. Only endpoint 0 counter register is locked when updated. The locking
mechanism does not apply to the count registers of other endpoints.
19.6 Endpoint Mode/Count Registers Update and Locking Mechanism
The contents of the endpoint mode and counter registers are updated, based on the packet flow diagram in Figure 19-5. Two
time points, UPDATE and SETUP, are shown in the same figure. The following activities occur at each time point:
Bit #76543210
Bit Name STALL Reserved Reserved ACK Mode Bit 3 Mode Bit 2 Mode Bit 1 Mode Bit 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Figure 19-3. USB Non-Control Endpoint Mode Registers
Bit #76543210
Bit Name Data 0/1 Toggle Data Valid Byte Count Bit
5
Byte Count Bit
4
Byte Count Bit
3
Byte Count Bit
2
Byte Count Bit
1
Byte Count Bit
0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Reset00000000
Figure 19-4. USB Endpoint Counter Registers