User`s guide

CY7C66013
C
CY7C66113
C
Document #: 38-08024 Rev. *B Page 41 of 61
1. Hardware detects the Resume, drives a K to the port, and generates the hub interrupt. The corresponding bit in the Resume
Status Register (0x4E) reads ‘1’ in this case.
2. Firmware responds to hub interrupt, and reads register 0x4E to determine the source of the Resume.
3. Firmware begins driving K on the port for 10 ms or more through register 0x4B.
4. Firmware clears the Selective Suspend bit for the port (0x4D), which clears the Resume bit (0x4E). This ends the hardware-driv-
en Resume, but the firmware-driven Resume continues. To prevent traffic being fed by the hub repeater to the port during or
just after the Resume, firmware should disable this port.
5. Firmware drives a timed SE0 on the port for two low-speed bit times as appropriate. Note: Firmware must disable interrupts
during this SE0 so the SE0 pulse isn’t inadvertently lengthened and appears as a bus reset to the downstream device.
6. Firmware drives a J on the port for one low-speed bit time, then it idles the port.
7. Firmware re-enables the port.
Resume when the hub is suspended typically involves these actions:
1. Hardware detects the Resume, drives a K on the upstream (which is then reflected to all downstream enabled ports), and
generates the hub interrupt.
2. The part comes out of suspend and the clocks start.
3. Once the clocks are stable, firmware execution resumes. An internal counter ensures that this takes at least 1 ms. Firmware
should check for Resume from any selectively suspended ports. If found, the Selective Suspend bit for the port should be
cleared; no other action is necessary.
4. The Resume ends when the host stops sending K from upstream. Firmware should check for changes to the Enable and
Connect Registers. If a port has become disabled but is still connected, an SE0 has been detected on the port. The port should
be treated as having been reset, and should be reported to the host as newly connected.
Firmware can choose to clear the Device Remote Wake-up bit (if set) to implement firmware timed states for port changes. All
allowed port changes wake the part. Then, the part can use internal timing to determine whether to take action or return to
suspend. If Device Remote Wake-up is set, automatic hardware assertions take place on Resume events.
18.5 USB Upstream Port Status and Control
USB status and control is regulated by the USB Status and Control Register, as shown in Figure 18-10. All bits in the register are
cleared during reset.
USB Status and Control ADDRESS 0x1F
Bits[2..0]: Control Action
Set to control action as per Table 18-2.The three control bits allow the upstream port to be driven manually by firmware.
For normal USB operation, all of these bits must be cleared. Table 18-2 shows how the control bits affect the upstream port.
Bit #76543210
Bit Name Endpoint Size Endpoint Mode D+ Upstream D– Upstream Bus Activity Control Action
Bit 2
Control Action
Bit 1
Control Action
Bit 0
Read/Write R/W R/W R R R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Figure 18-10. USB Status and Control Register
Table 18-2. Control Bit Definition for Upstream Port
Control Bits Control Action
000 Not Forcing (SIE Controls Driver)
001 Force D+[0] HIGH, D–[0] LOW
010 Force D+[0] LOW, D–[0] HIGH
011 Force SE0; D+[0] LOW, D–[0] LOW
100 Force D+[0] LOW, D–[0] LOW
101 Force D+[0] HiZ, D–[0] LOW
110 Force D+[0] LOW, D–[0] HiZ
111 Force D+[0] HiZ, D–[0] HiZ