User`s guide

CY7C66013
C
CY7C66113
C
Document #: 38-08024 Rev. *B Page 27 of 61
Bit [7..0]: Polarity bit x (x= 0..7)
1= Selects positive polarity (rising edge) that causes an interrupt (if enabled);
0 = Selects negative polarity (falling edge) that causes an interrupt (if enabled).
11.0 12-bit Free-running Timer
The 12-bit timer operates with a 1-µs tick, provides two interrupts (128 µs and 1.024 ms) and allows the firmware to directly time
events that are up to 4 ms in duration. The lower eight bits of the timer can be read directly by the firmware. Reading the lower
8 bits latches the upper four bits into a temporary register. When the firmware reads the upper four bits of the timer, it is actually
reading the count stored in the temporary register. The effect of this is to ensure a stable 12-bit timer value can be read, even
when the two reads are separated in time.
Timer LSB ADDRESS 0x24
Bit [7:0]: Timer lower eight bits
Timer MSB ADDRESS 0x25
Bit [3:0]: Timer higher nibble
Bit [7:4]: Reserved
12.0 I
2
C and HAPI Configuration Register
Internal hardware supports communication with external devices through two interfaces: a two-wire I
2
C-compatible, and a HAPI
for 1, 2, or 3 byte transfers. The I
2
C-compatible and HAPI functions, discussed in detail in Sections 13.0 and 14.0, share a
common configuration register (see Figure 12-1)
[3]
. All bits of this register are cleared on reset.
I
2
C Configuration ADDRESS 0x09
Bit #76543210
Bit Name Timer Bit 7 Timer Bit 6 Timer Bit 5 Timer Bit 4 Timer Bit 3 Timer Bit 2 Timer Bit 1 Timer Bit 0
Read/WriteRRRRRRRR
Reset 0 0 0 0 0 0 0 0
Figure 11-1. Timer LSB Register
Bit #76543210
Bit Name Reserved Reserved Reserved Reserved Timer Bit 11 Timer Bit 10 Timer Bit 9 Timer Bit 8
Read/Write - - - - R R R R
Reset 0 0 0 0 0 0 0 0
Figure 11-2. Timer MSB Register
Bit #76543210
Bit Name I
2
C Position Reserved LEMPTY
Polarity
DRDY
Polarity
Latch
Empty
Data
Ready
HAPI Port
Width Bit 1
HAPI Port
Width Bit 0
Read/Write R/W - R/W R/W R R R/W R/W
Reset 0 0 0 0 0 0 0 0
Figure 12-1. HAPI/I
2
C Configuration Register
10 9 7856432
1-MHz clock
1.024-ms interrupt
128-µs interrupt
To Timer Registers
8
1 011
L1 L0L2L
D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Figure 11-3. Timer Block Diagram
N
ote:
3. I
2
C-compatible function must be separately enabled, as described in Section 13.0.