User`s guide

CY7C66013
C
CY7C66113
C
Document #: 38-08024 Rev. *B Page 26 of 61
are set to ‘0’ when the device is suspended, that DAC input will float. The floating pin could result in excessive current consumption
by the device, unless an external load places the pin in a deterministic state.
DAC Port Data ADDRESS 0x30
Bit [1..0]: High Current Output 3.2 mA to 16 mA typical
1= I/O pin is an output pulled HGH through the 14-kΩ resistor. 0 = I/O pin is an input with an internal 14-kΩ pull-up resistor.
Bit [7..2]: Low Current Output 0.2 mA to 1 mA typical
1= I/O pin is an output pulled HGH through the 14-kΩ resistor. 0 = I/O pin is an input with an internal 14-kΩ pull-up resistor.
10.1 DAC Isink Registers
Each DAC I/O pin has an associated DAC Isink register to program the output sink current when the output is driven LOW. The
first Isink register (0x38) controls the current for DAC[0], the second (0x39) for DAC[1], and so on until the Isink register at 0x3F,
controls the current to DAC[7].
DAC Sink Register ADDRESS 0x38 –0x3F
Bit [3..0]: Isink [x] (x= 0..3)
Writing all ‘0’s to the Isink register causes 1/5 of the max current to flow through the DAC I/O pin. Writing all ‘1’s to the Isink
register provides the maximum current flow through the pin. The other 14 states of the DAC sink current are evenly spaced
between these two values.
Bit [7..4]: Reserved
10.2 DAC Port Interrupts
A DAC port interrupt can be enabled/disabled for each pin individually. The DAC Port Interrupt Enable register provides this
feature with an interrupt enable bit for each DAC I/O pin. All of the DAC Port Interrupt Enable register bits are cleared to ‘0’ during
a reset. All DAC pins share a common interrupt, as explained in Section 16.7.
DAC Port Interrupt ADDRESS 0x31
Bit [7..0]: Enable bit x (x= 0..7)
1 = Enables interrupts from the corresponding bit position; 0= Disables interrupts from the corresponding bit position
As an additional benefit, the interrupt polarity for each DAC pin is programmable with the DAC Port Interrupt Polarity register.
Writing a ‘0’ to a bit selects negative polarity (falling edge) that causes an interrupt (if enabled) if a falling edge transition occurs
on the corresponding input pin. Writing a ‘1’ to a bit in this register selects positive polarity (rising edge) that causes an interrupt
(if enabled) if a rising edge transition occurs on the corresponding input pin. All of the DAC Port Interrupt Polarity register bits are
cleared during a reset.
DAC IO Interrupt Polarity ADDRESS 0x32
Bit #76543210
Bit Name DAC[7] DAC[6] DAC[5] DAC[4] DAC[3] DAC[2] DAC[1] DAC[0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Reset11111111
Figure 10-2. DAC Port Data
Bit #76543210
Bit Name Reserved Reserved Reserved Reserved Isink[3] Isink[2] Isink[1] Isink[0]
Read/Write WWWW
Reset - - - - 0 0 0 0
Figure 10-3. DAC Sink Register
Bit #76543210
Bit Name Enable Bit 7 Enable Bit 6 Enable Bit 5 Enable Bit 4 Enable Bit 3 Enable Bit 2 Enable Bit 1 Enable Bit 0
Read/WriteWWWWWWWW
Reset00000000
Figure 10-4. DAC Port Interrupt Enable
Bit #76543210
Bit Name Polarity Bit 7 Polarity Bit 6 Polarity Bit 5 Polarity Bit 4 Polarity Bit 3 Polarity Bit 2 Polarity Bit 1 Polarity Bit 0
Read/WriteWWWWWWWW
Reset00000000
Figure 10-5. DAC Port Interrupt Polarity