Specifications

 2004 Microchip Technology Inc. Preliminary DS40044B-page 97
PIC16F627A/628A/648A
14.2.8 SPECIAL FEATURE: DUAL SPEED
OSCILLATOR MODES
A software programmable dual speed Oscillator mode
is provided when the PIC16F627A/628A/648A is
configured in the INTOSC Oscillator mode. This feature
allows users to dynamically toggle the oscillator speed
between 4 MHz and 37 kHz nominal in the INTOSC
mode. Applications that require low current power
savings, but cannot tolerate putting the part into Sleep,
may use this mode.
There is a time delay associated with the transition
between Fast and Slow oscillator speeds. This
Oscillator Speed Transition delay consists of two
existing clock pulses and eight new speed clock
pulses. During this Clock Speed Transition Delay the
System Clock is halted causing the processor to be
frozen in time. During this delay the Program Counter
and the Clock Out stop.
The OSCF bit in the PCON register is used to control Dual
Speed mode. See Section 4.2.2.6 "PCON Register",
Register 4-6.
14.3 Reset
The PIC16F627A/628A/648A differentiates between
various kinds of Reset:
a) Power-on Reset (POR)
b) MCLR
Reset during normal operation
c) MCLR Reset during Sleep
d) WDT Reset (normal operation)
e) WDT wake-up (Sleep)
f) Brown-out Reset (BOR)
Some registers are not affected in any Reset condition;
their status is unknown on POR and unchanged in any
other Reset. Most other registers are reset to a “Reset
state” on Power-on Reset, Brown-out Reset, MCLR
Reset, WDT Reset and MCLR Reset during Sleep.
They are not affected by a WDT wake-up, since this is
viewed as the resumption of normal operation. TO and
PD
bits are set or cleared differently in different Reset
situations as indicated in Table 14-4. These bits are
used in software to determine the nature of the Reset.
See Table 14-7 for a full description of Reset states of
all registers.
A simplified block diagram of the on-chip Reset circuit
is shown in Figure 14-6.
The MCLR
Reset path has a noise filter to detect and
ignore small pulses. See Table 17-7 for pulse width
specification.
FIGURE 14-6: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
S
R
Q
External
Reset
MCLR/
V
DD
OSC1/
WDT
Module
V
DD rise
detect
OST/PWRT
WDT
Time out
Power-on Reset
OST
PWRT
Chip_Reset
10-bit Ripple-counter
Reset
Enable OST
Enable PWRT
Sleep
See Table 14-3 for time out situations.
Note 1: This is a separate oscillator from the INTOSC/RC oscillator.
Brown-out
detect Reset
BOREN
CLKIN
Pin
V
PP Pin
10-bit Ripple-counter
Q
Schmitt Trigger Input
On-chip
(1)
OSC