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 2004 Microchip Technology Inc. Preliminary DS40044B

PIC16F627A/628A/648A

Data Sheet

Flash-Based 8-Bit CMOS

Microcontrollers with nanoWatt Technology

Summary of content (168 pages)

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PIC16F627A/628A/648A Data Sheet Flash-Based 8-Bit CMOS Microcontrollers with nanoWatt Technology  2004 Microchip Technology Inc.
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Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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PIC16F627A/628A/648A 18-pin Flash-Based 8-Bit CMOS Microcontrollers with nanoWatt Technology High Performance RISC CPU: Low Power Features: • • • • • • Standby Current: - 100 nA @ 2.0V, typical • Operating Current: - 12 µA @ 32 kHz, 2.0V, typical - 120 µA @ 1 MHz, 2.0V, typical • Watchdog Timer Current - 1 µA @ 2.0V, typical • Timer1 oscillator current: - 1.2 µA @ 32 kHz, 2.0V, typical • Dual Speed Internal Oscillator: - Run-time selectable between 4 MHz and 37 kHz - 4 µs wake-up from Sleep, 3.
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PIC16F627A/628A/648A Pin Diagrams PDIP, SOIC 1 18 RA1/AN1 RA3/AN3/CMP1 2 17 RA0/AN0 16 RA7/OSC1/CLKIN 15 RA6/OSC2/CLKOUT 14 VDD 13 RB7/T1OSI/PGD 3 RA5/MCLR/VPP 4 RB0/INT 6 RB1/RX/DT 7 12 RB6/T1OSO/T1CKI/PGC RB2/TX/CK 8 11 RB5 RB3/CCP1 9 10 RB4/PGM RA5/MCLR/VPP 8 9 10 NC 11 12 RB4/PGM 13 RB5 NC 14 1 21 NC 2 20 VSS 3 19 NC 4 PIC16F627A/628A 18 NC PIC16F648A VSS 17 5 NC 6 16 RB0/INT 7 15 DS40044B-page 2 RA7/OSC1/CLKIN RA6/OSC2/CLKOUT VDD VDD RB7/T1OSI/PGD RB6/T1OSO/T1CKI/PG
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PIC16F627A/628A/648A Table of Contents 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0 14.0 15.0 16.0 17.0 18.0 19.0 General Description...................................................................................................................................................................... 5 PIC16F627A/628A/648A Device Varieties ................................................................................................................................... 7 Architectural Overview ...
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PIC16F627A/628A/648A NOTES: DS40044B-page 4 Preliminary  2004 Microchip Technology Inc.
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PIC16F627A/628A/648A 1.0 GENERAL DESCRIPTION HS is for High-Speed crystals. The EC mode is for an external clock source. The PIC16F627A/628A/648A are 18-Pin Flash-based members of the versatile PIC16CXX family of low cost, high performance, CMOS, fully-static, 8-bit microcontrollers. All PICmicro® microcontrollers employ an advanced RISC architecture. The PIC16F627A/628A/648A have enhanced core features, eight-level deep stack, and multiple internal and external interrupt sources.
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PIC16F627A/628A/648A NOTES: DS40044B-page 6 Preliminary  2004 Microchip Technology Inc.
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PIC16F627A/628A/648A 2.0 PIC16F627A/628A/648A DEVICE VARIETIES A variety of frequency ranges and packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in the PIC16F627A/628A/648A Product Identification System, at the end of this data sheet. When placing orders, please use this page of the data sheet to specify the correct part number. 2.
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PIC16F627A/628A/648A NOTES: DS40044B-page 8 Preliminary  2004 Microchip Technology Inc.
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PIC16F627A/628A/648A 3.0 ARCHITECTURAL OVERVIEW The high performance of the PIC16F627A/628A/648A family can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC16F627A/628A/648A uses a Harvard architecture, in which program and data are accessed from separate memories using separate busses. This improves bandwidth over traditional Von Neumann architecture where program and data are fetched from the same memory.
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PIC16F627A/628A/648A FIGURE 3-1: BLOCK DIAGRAM 13 Program Memory RAM File Registers 8-Level Stack (13-bit) Program Bus 14 8 Data Bus Program Counter Flash RAM Addr (1) PORTA 9 Addr MUX Instruction reg Direct Addr 7 8 RA0/AN0 RA1/AN1 RA2/AN2/VREF RA3/AN3/CMP1 RA4/T0CK1/CMP2 RA5/MCLR/VPP RA6/OSC2/CLKOUT RA7/OSC1/CLKIN Indirect Addr FSR reg Status Reg 8 3 Power-up Timer Instruction Decode & Control Timing Generation OSC1/CLKIN OSC2/CLKOUT Oscillator Start-up Timer MUX RB0/INT RB1/RX/DT R
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PIC16F627A/628A/648A TABLE 3-2: PIC16F627A/628A/648A PINOUT DESCRIPTION Name RA0/AN0 RA1/AN1 RA2/AN2/VREF RA3/AN3/CMP1 RA4/T0CKI/CMP2 RA5/MCLR/VPP RA6/OSC2/CLKOUT RA7/OSC1/CLKIN Function Input Type Output Type CMOS Description RA0 ST Bidirectional I/O port AN0 AN — RA1 ST CMOS AN1 AN — RA2 ST CMOS AN2 AN — Analog comparator input VREF — AN VREF output RA3 ST CMOS AN3 AN — CMP1 — CMOS Comparator 1 output RA4 ST OD Bidirectional I/O port T0CKI ST — Timer0 clo
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PIC16F627A/628A/648A TABLE 3-2: PIC16F627A/628A/648A PINOUT DESCRIPTION Name RB4/PGM Function Input Type Output Type Description RB4 TTL CMOS PGM ST — RB5 RB5 TTL CMOS Bidirectional I/O port. Interrupt-on-pin change. Can be software programmed for internal weak pull-up. RB6/T1OSO/T1CKI/PGC RB6 TTL CMOS Bidirectional I/O port. Interrupt-on-pin change. Can be software programmed for internal weak pull-up. T1OSO — XTAL Timer1 oscillator output. T1CKI ST — Timer1 clock input.
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PIC16F627A/628A/648A 3.1 Clocking Scheme/Instruction Cycle 3.2 Instruction Flow/Pipelining An instruction cycle consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g.
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PIC16F627A/628A/648A NOTES: DS40044B-page 14 Preliminary  2004 Microchip Technology Inc.
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PIC16F627A/628A/648A 4.0 MEMORY ORGANIZATION 4.2 4.1 Program Memory Organization The data memory (Figure 4-2 and Figure 4-3) is partitioned into four banks, which contain the General Purpose Registers (GPR’s) and the Special Function Registers (SFR). The SFR’s are located in the first 32 locations of each Bank. There are General Purpose Registers implemented as static RAM in each Bank. Table 4-1 lists the General Purpose Register available in each of the four banks.
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PIC16F627A/628A/648A FIGURE 4-2: DATA MEMORY MAP OF THE PIC16F627A AND PIC16F628A File Address Indirect addr.(1) 00h Indirect addr.(1) 80h Indirect addr.(1) 100h Indirect addr.
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PIC16F627A/628A/648A FIGURE 4-3: DATA MEMORY MAP OF THE PIC16F648A File Address Indirect addr.(1) 00h Indirect addr.(1) 80h Indirect addr.(1) 100h Indirect addr.
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PIC16F627A/628A/648A 4.2.2 SPECIAL FUNCTION REGISTERS The SFRs are registers used by the CPU and Peripheral functions for controlling the desired operation of the device (Table 4-3). These registers are static RAM. The special registers can be classified into two sets (core and peripheral). The SFRs associated with the “core” functions are described in this section. Those related to the operation of the peripheral features are described in the section of that peripheral feature.
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PIC16F627A/628A/648A TABLE 4-4: Address SPECIAL FUNCTION REGISTERS SUMMARY BANK1 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Details POR on Reset(1) Page Bank 1 80h INDF 81h OPTION 82h PCL 83h STATUS 84h FSR Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU INTEDG T0CS T0SE PSA PS2 PS1 xxxx xxxx PS0 Program Counter's (PC) Least Significant Byte IRP RP1 RP0 TO PD Z DC C Indirect data memory address point
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PIC16F627A/628A/648A TABLE 4-5: Address SPECIAL FUNCTION REGISTERS SUMMARY BANK2 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Reset(1) Details on Page Bank 2 100h INDF 101h 102h TMR0 PCL 103h STATUS 104h FSR Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx Timer0 module’s Register xxxx xxxx Program Counter's (PC) Least Significant Byte IRP RP1 RP0 TO 0000 0000 PD Z DC C Indirect data memory address poin
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PIC16F627A/628A/648A TABLE 4-6: Address SPECIAL FUNCTION REGISTERS SUMMARY BANK3 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Reset(1) Details on Page Bank 3 180h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 28 181h 182h OPTION PCL INTEDG T0CS T0SE RBPU Program Counter's (PC) Least Significant Byte PSA 1111 1111 23 0000 0000 28 183h STATUS IRP PD 0001 1xxx 22 184h FSR Indirect data memory a
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PIC16F627A/628A/648A 4.2.2.1 Status Register The Status Register, shown in Register 4-1, contains the arithmetic status of the ALU; the Reset status and the bank select bits for data memory (SRAM). The Status Register can be the destination for any instruction, like any other register. If the Status Register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic.
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PIC16F627A/628A/648A 4.2.2.2 OPTION Register Note: The OPTION register is a readable and writable register, which contains various control bits to configure the TMR0/WDT prescaler, the external RB0/INT interrupt, TMR0 and the weak pull-ups on PORTB. REGISTER 4-2: To achieve a 1:1 prescaler assignment for TMR0, assign the prescaler to the WDT (PSA = 1). See Section 6.3.1 "Switching Prescaler Assignment".
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PIC16F627A/628A/648A 4.2.2.3 INTCON Register Note: The INTCON register is a readable and writable register, which contains the various enable and flag bits for all interrupt sources except the comparator module. See Section 4.2.2.4 "PIE1 Register" and Section 4.2.2.5 "PIR1 Register" for a description of the comparator enable and flag bits.
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PIC16F627A/628A/648A 4.2.2.4 PIE1 Register This register contains interrupt enable bits.
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PIC16F627A/628A/648A 4.2.2.5 PIR1 Register Note: This register contains interrupt flag bits. REGISTER 4-5: Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
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PIC16F627A/628A/648A 4.2.2.6 PCON Register The PCON register contains flag bits to differentiate between a Power-on Reset, an external MCLR Reset, WDT Reset or a Brown-out Reset. REGISTER 4-6: Note: BOR is unknown on Power-on Reset. It must then be set by the user and checked on subsequent Resets to see if BOR is cleared, indicating a brown-out has occurred.
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PIC16F627A/628A/648A 4.3 PCL and PCLATH The program counter (PC) is 13-bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<12:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 4-4 shows the two situations for loading the PC. The upper example in Figure 4-4 shows how the PC is loaded on a write to PCL (PCLATH<4:0> → PCH).
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PIC16F627A/628A/648A FIGURE 4-5: Status Register RP1 RP0 bank select DIRECT/INDIRECT ADDRESSING PIC16F627A/628A/648A Status Register Direct Addressing 6 from opcode 0 IRP Indirect Addressing 7 bank select location select 00 01 10 FSR Register 0 location select 11 00h 180h RAM File Registers 7Fh 1FFh Bank 0 Note: Bank 1 Bank 2 Bank 3 For memory map detail see Figure 4-3, Figure 4-2 and Figure 4-1.  2004 Microchip Technology Inc.
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PIC16F627A/628A/648A NOTES: DS40044B-page 30 Preliminary  2004 Microchip Technology Inc.
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PIC16F627A/628A/648A 5.0 I/O PORTS The PIC16F627A/628A/648A have two ports, PORTA and PORTB. Some pins for these I/O ports are multiplexed with alternate functions for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. 5.1 IPORTA and TRISA Registers PORTA is an 8-bit wide latch. RA4 is a Schmitt Trigger input and an open drain output. Port RA4 is multiplexed with the T0CKI clock input.
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PIC16F627A/628A/648A FIGURE 5-2: Data Bus BLOCK DIAGRAM OF RA2/VREF PIN D WR PORTA Q CK VDD Q Data Latch D Q RA2 Pin WR TRISA CK Analog Input Mode (CMCON Reg.) Q TRIS Latch RD TRISA VSS Schmitt Trigger Input Buffer Q D EN RD PORTA To Comparator VROE VREF FIGURE 5-3: Data Bus BLOCK DIAGRAM OF THE RA3/AN3 PIN Comparator Mode = 110 (CMCON Reg.) D VDD Q Comparator Output WR PORTA 1 CK Q Data Latch D 0 Q RA3 Pin WR TRISA CK Analog Input Mode (CMCON Reg.
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PIC16F627A/628A/648A FIGURE 5-4: Data Bus BLOCK DIAGRAM OF RA4/T0CKI PIN Comparator Mode = 110 (CMCON Reg.
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PIC16F627A/628A/648A FIGURE 5-7: BLOCK DIAGRAM OF RA7/OSC1/CLKIN PIN To Clock Circuits VDD Data Bus WR PORTA D Q RA7/OSC1/CLKIN Pin CK Q Data Latch D WR TRISA CK VSS Q Q TRIS Latch RD TRISA FOSC = 100, 101(1) Q D Schmitt Trigger Input Buffer EN RD PORTA Note 1: INTOSC with CLKOUT, and INTOSC with I/O. DS40044B-page 34 Preliminary  2004 Microchip Technology Inc.
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PIC16F627A/628A/648A TABLE 5-1: PORTA FUNCTIONS Name RA0/AN0 RA1/AN1 RA2/AN2/VREF RA3/AN3/CMP1 RA4/T0CKI/CMP2 RA5/MCLR/VPP RA6/OSC2/CLKOUT Function Input Type Output Type RA0 AN0 RA1 AN1 RA2 AN2 VREF RA3 AN3 CMP1 RA4 T0CKI CMP2 ST AN ST AN ST AN — ST AN — ST ST — CMOS — CMOS — CMOS — AN CMOS — CMOS OD — OD RA5 ST — MCLR ST — VPP RA6 OSC2 HV ST — — CMOS XTAL CLKOUT RA7/OSC1/CLKIN Legend: RA7 OSC1 CLKIN O = Output — = Not used TTL = TTL Input  2004 Microchip Technology Inc.
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PIC16F627A/628A/648A TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA(1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Value on All Other Resets PORTA RA7 RA6 RA5(2) RA4 RA3 RA2 RA1 RA0 xxxx 0000 qqqu 0000 85h TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111 1Fh CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 0000 0000 9Fh VRCON VREN VROE VRR — VR3 VR2 VR1 VR0 000- 0000 000- 0000 Address 05h
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PIC16F627A/628A/648A FIGURE 5-8: BLOCK DIAGRAM OF RB0/INT PIN FIGURE 5-9: BLOCK DIAGRAM OF RB1/RX/DT PIN VDD VDD RBPU Weak P Pull-up VDD RBPU P Weak Pull-up SPEN VDD USART Data Output Data Bus WR PORTB Data Bus D Q RB0/INT CK WR TRISB CK Q D Q CK Q 0 RB1/ RX/DT Data Latch VSS Data Latch D WR PORTB Q 1 WR TRISB Q D Q CK Q VSS TRIS Latch Peripheral OE(1) TRIS Latch TTL Input Buffer RD TRISB TTL Input Buffer RD TRISB Q Q D D EN RD PORTB EN EN USART Receive Input R
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PIC16F627A/628A/648A FIGURE 5-10: BLOCK DIAGRAM OF RB2/TX/CK PIN FIGURE 5-11: VDD Weak P Pull-up VDD RBPU SPEN USART TX/CK Output Data Bus WR PORTB Q CK Q RB2/ TX/CK 0 WR TRISB Q CK Q CCP1CON 0 Data Bus WR PORTB Data Latch D VDD Weak P Pull-up VDD RBPU CCP output 1 D BLOCK DIAGRAM OF RB3/CCP1 PIN D Q CK Q Data Latch VSS WR TRISB TRIS Latch D Q CK Q VSS TRIS Latch Peripheral OE(1) Peripheral OE(2) TTL Input Buffer RD TRISB Q TTL Input Buffer RD TRISB D Q EN RD POR
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PIC16F627A/628A/648A FIGURE 5-12: BLOCK DIAGRAM OF RB4/PGM PIN VDD RBPU P weak pull-up Data Bus WR PORTB D Q CK Q VDD Data Latch WR TRISB D Q CK Q RB4/PGM VSS TRIS Latch RD TRISB LVP (Configuration Bit) RD PORTB PGM input TTL input buffer Schmitt Trigger Q D EN Q1 Set RBIF Q From other RB<7:4> pins D EN Note: Q3 The low voltage programming disables the interrupt-on-change and the weak pull-ups on RB4.  2004 Microchip Technology Inc.
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PIC16F627A/628A/648A FIGURE 5-13: BLOCK DIAGRAM OF RB5 PIN VDD RBPU weak VDD P pull-up Data Bus D Q CK Q RB5 pin WR PORTB Data Latch VSS D Q CK Q WR TRISB TRIS Latch TTL input buffer RD TRISB Q D RD PORTB EN Q1 Set RBIF Q From other RB<7:4> pins D EN DS40044B-page 40 Preliminary Q3  2004 Microchip Technology Inc.
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PIC16F627A/628A/648A FIGURE 5-14: BLOCK DIAGRAM OF RB6/T1OSO/T1CKI PIN VDD RBPU P weak pull-up Data Bus WR PORTB D Q CK Q VDD Data Latch WR TRISB D Q CK Q RB6/ T1OSO/ T1CKI pin VSS TRIS Latch RD TRISB T1OSCEN TTL input buffer RD PORTB TMR1 Clock From RB7 Schmitt Trigger TMR1 oscillator Serial programming clock Q D EN Q1 Set RBIF From other RB<7:4> pins Q D Q3 EN  2004 Microchip Technology Inc.
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PIC16F627A/628A/648A FIGURE 5-15: BLOCK DIAGRAM OF THE RB7/T1OSI PIN VDD RBPU P weak pull-up TMR1 oscillator To RB6 VDD Data Bus WR PORTB D Q CK Q RB7/T1OSI pin Data Latch WR TRISB D Q CK Q VSS TRIS Latch RD TRISB T10SCEN TTL input buffer RD PORTB Serial programming input Schmitt Trigger Q D EN Q1 Set RBIF From other RB<7:4> pins Q D EN DS40044B-page 42 Preliminary Q3  2004 Microchip Technology Inc.
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PIC16F627A/628A/648A TABLE 5-3: PORTB FUNCTIONS Name Function Input Type Output Type RB0/INT RB0 TTL CMOS RB1/RX/DT INT RB1 ST TTL — CMOS RB2/TX/CK RX DT RB2 TX CK RB3/CCP1 RB3 RB4/PGM CCP1 RB4 RB5 RB6/T1OSO/T1CKI/ PGC RB6 T1OSO T1CKI PGC RB7 RB7/T1OSI/PGD T1OSI PGD Legend: O = Output — = Not used TTL = TTL Input TABLE 5-4: Bidirectional I/O port. Can be software programmed for internal weak pull-up. External interrupt. Bidirectional I/O port.
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PIC16F627A/628A/648A 5.3 I/O Programming Considerations 5.3.1 EXAMPLE 5-2: BIDIRECTIONAL I/O PORTS Any instruction that writes, operates internally as a read followed by a write operation. The BCF and BSF instructions, for example, read the register into the CPU, execute the bit operation and write the result back to the register. Caution must be used when these instructions are applied to a port with both inputs and outputs defined.
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PIC16F627A/628A/648A 6.0 TIMER0 MODULE 6.2 The Timer0 module timer/counter has the following features: • • • • • • 8-bit timer/counter Read/Write capabilities 8-bit software programmable prescaler Internal or external clock select Interrupt on overflow from FFh to 00h Edge select for external clock Timer mode is selected by clearing the T0CS bit (OPTION<5>). In Timer mode, the TMR0 register value will increment every instruction cycle (without prescaler).
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PIC16F627A/628A/648A 6.3 Timer0 Prescaler The PSA and PS2:PS0 bits (OPTION<3:0>) determine the prescaler assignment and prescale ratio. An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the Watchdog Timer. A prescaler assignment for the Timer0 module means that there is no postscaler for the Watchdog Timer, and vice-versa. FIGURE 6-1: When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g., CLRF 1, MOVWF 1, BSF 1, x....etc.
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PIC16F627A/628A/648A 6.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control (i.e., it can be changed “on the fly” during program execution). Use the instruction sequences shown in Example 6-1 when changing the prescaler assignment from Timer0 to WDT, to avoid an unintended device Reset.
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PIC16F627A/628A/648A 7.0 TIMER1 MODULE The Operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). The Timer1 module is a 16-bit timer/counter consisting of two 8-bit registers (TMR1H and TMR1L) which are readable and writable. The TMR1 register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The Timer1 Interrupt, if enabled, is generated on overflow of the TMR1 register pair which latches the interrupt flag bit TMR1IF (PIR1<0>).
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PIC16F627A/628A/648A 7.1 7.2.1 Timer1 Operation in Timer Mode Timer mode is selected by clearing the TMR1CS (T1CON<1>) bit. In this mode, the input clock to the timer is FOSC/4. The synchronize control bit T1SYNC (T1CON<2>) has no effect since the internal clock is always in sync. 7.2 Timer1 Operation in Synchronized Counter Mode Counter mode is selected by setting bit TMR1CS.
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PIC16F627A/628A/648A 7.3 EXAMPLE 7-1: Timer1 Operation in Asynchronous Counter Mode If control bit T1SYNC (T1CON<2>) is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks. The timer will continue to run during Sleep and can generate an interrupt on overflow, which will wake-up the processor. However, special precautions in software are needed to read/write the timer (Section 7.3.
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PIC16F627A/628A/648A 7.4 Timer1 Oscillator 7.5 A crystal oscillator circuit is built in between pins T1OSI (input) and T1OSO (amplifier output). It is enabled by setting control bit T1OSCEN (T1CON<3>). It will continue to run during Sleep. It is primarily intended for a 32.768 kHz watch crystal. Table 7-1 shows the capacitor selection for the Timer1 oscillator. If the CCP1 module is configured in Compare mode to generate a “special event trigger” (CCP1M3:CCP1M0 = 1011), this signal will Reset Timer1.
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PIC16F627A/628A/648A 8.0 TIMER2 MODULE 8.1 Timer2 is an 8-bit timer with a prescaler and a postscaler. It can be used as the PWM time-base for PWM mode of the CCP module. The TMR2 register is readable and writable, and is cleared on any device Reset. The input clock (FOSC/4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits T2CKPS1:T2CKPS0 (T2CON<1:0>). The Timer2 module has an 8-bit period register PR2.
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PIC16F627A/628A/648A REGISTER 8-1: T2CON: TIMER2 CONTROL REGISTER (ADDRESS: 12h) U-0 R/W-0 — R/W-0 R/W-0 TOUTPS3 TOUTPS2 TOUTPS1 R/W-0 R/W-0 TOUTPS0 R/W-0 R/W-0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6-3 TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale Value 0001 = 1:2 Postscale Value • • • 1111 = 1:16 Postscale bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select b
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PIC16F627A/628A/648A NOTES: DS40044B-page 54 Preliminary  2004 Microchip Technology Inc.
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PIC16F627A/628A/648A 9.0 CAPTURE/COMPARE/PWM (CCP) MODULE TABLE 9-1: The CCP (Capture/Compare/PWM) module contains a 16-bit register which can operate as a 16-bit capture register, as a 16-bit compare register or as a PWM master/slave Duty Cycle register. Table 9-1 shows the timer resources of the CCP module modes.
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PIC16F627A/628A/648A 9.1 9.1.4 Capture Mode In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin RB3/CCP1. An event is defined as: • • • • Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge An event is selected by control bits CCP1M3:CCP1M0 (CCP1CON<3:0>). When a capture is made, the interrupt request flag bit CCP1IF (PIR1<2>) is set. It must be cleared in software.
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PIC16F627A/628A/648A 9.2.1 CCP PIN CONFIGURATION 9.2.3 The user must configure the RB3/CCP1 pin as an output by clearing the TRISB<3> bit. Note: 9.2.2 When generate software interrupt is chosen the CCP1 pin is not affected. Only a CCP interrupt is generated (if enabled). Clearing the CCP1CON register will force the RB3/CCP1 compare output latch to the default low level. This is not the data latch. 9.2.4 The special event trigger output of CCP1 resets the TMR1 register pair.
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PIC16F627A/628A/648A 9.3 PWM Mode In Pulse Width Modulation (PWM) mode, the CCP1 pin produces up to a 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the PORTB data latch, the TRISB<3> bit must be cleared to make the CCP1 pin an output. Note: A PWM output (Figure 9-4) has a time base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (frequency = 1/period).
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PIC16F627A/628A/648A 9.3.2 PWM DUTY CYCLE Maximum PWM resolution (bits) for a given PWM frequency: The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON<5:4> bits. Up to 10-bit resolution is available: the CCPR1L contains the eight MSbs and the CCP1CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>.
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PIC16F627A/628A/648A NOTES: DS40044B-page 60 Preliminary  2004 Microchip Technology Inc.
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PIC16F627A/628A/648A 10.0 COMPARATOR MODULE The CMCON register, shown in Register 10-1, controls the comparator input and output multiplexers. A block diagram of the comparator is shown in Figure 10-1. The Comparator module contains two analog comparators. The inputs to the comparators are multiplexed with the RA0 through RA3 pins. The on-chip Voltage Reference (Section 11.0 "Voltage Reference Module") can also be an input to the comparators.
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PIC16F627A/628A/648A 10.1 Comparator Configuration If the Comparator mode is changed, the comparator output level may not be valid for the specified mode change delay shown in Table 17-2. There are eight modes of operation for the comparators. The CMCON register is used to select the mode. Figure 10-1 shows the eight possible modes. The TRISA register controls the data direction of the comparator pins for each mode.
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PIC16F627A/628A/648A The code example in Example 10-1 depicts the steps required to configure the Comparator module. RA3 and RA4 are configured as digital output. RA0 and RA1 are configured as the V- inputs and RA2 as the V+ input to both comparators. EXAMPLE 10-1: FLAG_REG CLRF CLRF MOVF ANDLW IORWF MOVLW MOVWF BSF MOVLW MOVWF BCF CALL MOVF BCF BSF BSF BCF BSF BSF 10.
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PIC16F627A/628A/648A 10.5 Comparator Outputs The comparator outputs are read through the CMCON register. These bits are read only. The comparator outputs may also be directly output to the RA3 and RA4 I/O pins. When the CM<2:0> = 110 or 001, multiplexors in the output path of the RA3 and RA4/T0CK1 pins will switch and the output of each pin will be the unsynchronized output of the comparator.
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PIC16F627A/628A/648A 10.6 Comparator Interrupts 10.7 The comparator interrupt flag is set whenever there is a change in the output value of either comparator. Software will need to maintain information about the status of the output bits, as read from CMCON<7:6>, to determine the actual change that has occurred. The CMIF bit, PIR1<6>, is the comparator interrupt flag. The CMIF bit must be Reset by clearing ‘0’.
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PIC16F627A/628A/648A FIGURE 10-4: ANALOG INPUT MODE VDD VT = 0.6V RS < 10 K RIC AIN CPIN 5 pF VA VT = 0.
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PIC16F627A/628A/648A 11.0 VOLTAGE REFERENCE MODULE The equations used to calculate the output of the Voltage Reference are as follows: if VRR = 1: The Voltage Reference is a 16-tap resistor ladder network that provides a selectable voltage reference. The resistor ladder is segmented to provide two ranges of VREF values and has a power-down function to conserve power when the reference is not being used. The VRCON register controls the operation of the reference as shown in Figure 11-1.
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PIC16F627A/628A/648A EXAMPLE 11-1: MOVLW MOVWF BSF MOVLW MOVWF MOVLW MOVWF BCF CALL 11.2 VOLTAGE REFERENCE CONFIGURATION 0x02 CMCON STATUS,RP0 0x07 TRISA 0xA6 VRCON STATUS,RP0 DELAY10 11.4 A device Reset disables the Voltage Reference by clearing bit VREN (VRCON<7>). This Reset also disconnects the reference from the RA2 pin by clearing bit VROE (VRCON<6>) and selects the high voltage range by clearing bit VRR (VRCON<5>). The VREF value select bits, VRCON<3:0>, are also cleared.
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PIC16F627A/628A/648A 12.0 UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (USART) MODULE The USART can be configured in the following modes: • Asynchronous (full-duplex) • Synchronous - Master (half-duplex) • Synchronous - Slave (half-duplex) The Universal Synchronous Asynchronous Receiver Transmitter (USART) is also known as a Serial Communications Interface or SCI.
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PIC16F627A/628A/648A REGISTER 12-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS: 18h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADEN FERR OERR RX9D bit 7 bit 0 bit 7 SPEN: Serial Port Enable bit (Configures RB1/RX/DT and RB2/TX/CK pins as serial port pins when bits TRISB<2:1> are set) 1 = Serial port enabled 0 = Serial port disabled bit 6 RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable
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PIC16F627A/628A/648A 12.1 EXAMPLE 12-1: USART Baud Rate Generator (BRG) CALCULATING BAUD RATE ERROR The BRG supports both the Asynchronous and Synchronous modes of the USART. It is a dedicated 8bit baud rate generator. The SPBRG register controls the period of a free running 8-bit timer. In Asynchronous mode bit BRGH (TXSTA<2>) also controls the baud rate. In Synchronous mode bit BRGH is ignored.
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PIC16F627A/628A/648A TABLE 12-3: BAUD RATE (K) 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW BAUD RATE (K) BAUD RATES FOR SYNCHRONOUS MODE FOSC = 20 MHz KBAUD ERROR NA NA NA NA 19.53 76.92 96.15 294.1 500 5000 19.53 — — — — +1.73% +0.16% +0.16% -1.96 0 — — FOSC = 7.15909 MHz SPBRG 16 MHz value KBAUD (decimal) — — — — 255 64 51 16 9 0 255 NA NA NA NA 19.23 76.92 95.24 307.69 500 4000 15.625 SPBRG 5.0688 MHz value KBAUD (decimal) ERROR — — — — +0.16% +0.16% -0.79% +2.
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PIC16F627A/628A/648A TABLE 12-4: BAUD RATE (K) 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW BAUD RATE (K) 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW BAUD RATE (K) 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0) FOSC = 20 MHz KBAUD ERROR NA 1.221 2.404 9.469 19.53 78.13 104.2 312.5 NA 312.5 1.221 — +1.73% +0.16% -1.36% +1.73% +1.73% +8.51% +4.17% — — — FOSC = 7.15909 MHz KBAUD ERROR NA 1.203 2.380 9.322 18.64 NA NA NA NA 111.9 0.437 — +0.23% -0.83% -2.
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PIC16F627A/628A/648A TABLE 12-5: BAUD RATE (K) 9600 19200 38400 57600 115200 250000 625000 1250000 BAUD RATE (K) 9600 19200 38400 57600 115200 250000 625000 1250000 BAUD RATE (K) 9600 19200 38400 57600 115200 250000 625000 1250000 BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1) FOSC = 20 MHz KBAUD ERROR 9.615 19.230 37.878 56.818 113.636 250 625 1250 +0.16% +0.16% -1.36% -1.36% -1.36% 0 0 0 FOSC = 7.16 MHz KBAUD ERROR 9.520 19.454 37.286 55.930 111.860 NA NA NA -0.83% +1.32% -2.90% -2.90% -2.
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PIC16F627A/628A/648A The data on the RB1/RX/DT pin is sampled three times by a majority detect circuit to determine if a high or a low level is present at the RX pin. If bit BRGH (TXSTA<2>) is clear (i.e., at the low baud rates), the sampling is done on the seventh, eighth and ninth falling edges of a x16 clock (Figure 12-3). If bit BRGH is set (i.e.
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PIC16F627A/628A/648A FIGURE 12-4: RX PIN SAMPLING SCHEME, BRGH = 0 OR BRGH = 1 RX (RB1/RX/DT pin) Start bit bit 0 Baud CLK for all but Start bit Baud CLK x16 CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 Samples 12.2 USART Asynchronous Mode In this mode, the USART uses standard non-return-tozero (NRZ) format (one Start bit, eight or nine data bits and one Stop bit). The most common data format is 8-bit.
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PIC16F627A/628A/648A FIGURE 12-5: USART TRANSMIT BLOCK DIAGRAM Data Bus TXIF TXREG register TXIE 8 MSb (8) LSb 0 ² ² ² Pin Buffer and Control TSR register RB2/TX/CK pin Interrupt TXEN Baud Rate CLK TRMT SPEN SPBRG TX9 Baud Rate Generator TX9D Follow these steps when setting up an Asynchronous Transmission: 1. 2. 3. 4. 5. 6. 7. 8.
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PIC16F627A/628A/648A FIGURE 12-7: ASYNCHRONOUS TRANSMISSION (BACK TO BACK) Write to TXREG Word 1 BRG output (shift clock) RB2/TX/CK (pin) Start Bit TXIF bit (interrupt reg. flag) TRMT bit (Transmit shift reg. empty flag) Note: TABLE 12-6: Address Name Word 2 Bit 0 Bit 1 WORD 1 Bit 7/8 Start Bit Stop Bit Bit 0 WORD 2 WORD 1 Transmit Shift Reg. WORD 2 Transmit Shift Reg. . timing diagram shows two consecutive transmissions.
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PIC16F627A/628A/648A 12.2.2 USART ASYNCHRONOUS RECEIVER double buffered register, (i.e., it is a two deep FIFO). It is possible for two bytes of data to be received and transferred to the RCREG FIFO and a third byte begin shifting to the RSR register. On the detection of the Stop bit of the third byte, if the RCREG register is still full then overrun error bit OERR (RCSTA<1>) will be set. The word in the RSR will be lost. The RCREG register can be read twice to retrieve the two bytes in the FIFO.
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PIC16F627A/628A/648A FIGURE 12-9: ASYNCHRONOUS RECEPTION WITH ADDRESS DETECT RB1/RX/DT (PIN) START BIT BIT0 BIT1 BIT8 STOP BIT START BIT BIT0 BIT8 STOP BIT RCV SHIFT REG RCV BUFFER REG BIT8 = 0, DATA BYTE BIT8 = 1, ADDRESS BYTE READ RCV BUFFER REG RCREG WORD 1 RCREG RCIF (INTERRUPT FLAG) ‘1’ ADEN = 1 (ADDRESS MATCH ENABLE) Note: ‘1’ This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG (Receive Buffer) because ADEN = 1 and Bit 8 = 0.
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PIC16F627A/628A/648A Follow these steps when setting up an Asynchronous Reception: 1. TRISB<1> bit needs to be set and TRISB<2> bit cleared in order to configure pins RB2/TX/CK and RB1/RX/DT as the Universal Synchronous Asynchronous Receiver Transmitter pins. 2. Initialize the SPBRG register for the appropriate baud rate. If a high-speed baud rate is desired, set bit BRGH. (Section 12.1 "USART Baud Rate Generator (BRG)"). 3. Enable the asynchronous serial port by clearing bit SYNC, and setting bit SPEN. 4.
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PIC16F627A/628A/648A 12.3 USART Address Detect Function 12.3.1 The ADEN bit will only take effect when the receiver is configured in 9-bit mode (RX9 = ‘1’). When ADEN is disabled (= ‘0’), all data bytes are received and the 9th bit can be used as the parity bit. USART 9-BIT RECEIVER WITH ADDRESS DETECT The receive block diagram is shown in Figure 12-8. When the RX9 bit is set in the RCSTA register, 9 bits are received and the ninth bit is placed in the RX9D bit of the RCSTA register.
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PIC16F627A/628A/648A 12.4 USART Synchronous Master Mode In Synchronous Master mode, the data is transmitted in a half-duplex manner, (i.e., transmission and reception do not occur at the same time). When transmitting data, the reception is inhibited and vice versa. Synchronous mode is entered by setting bit SYNC (TXSTA<4>). In addition enable bit SPEN (RCSTA<7>) is set in order to configure the RB2/TX/CK and RB1/RX/DT I/O pins to CK (clock) and DT (data) lines respectively.
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PIC16F627A/628A/648A TABLE 12-9: Address 0Ch 18h 19h 8Ch 98h REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Name Bit 7 Bit 6 Bit 5 Bit 4 PIR1 EEIF CMIF RCIF TXIF RCSTA SPEN RX9 SREN CREN TXREG USART Transmit data register PIE1 EEIE CMIE RCIE TXIE TXSTA CSRC TX9 TXEN SYNC Bit 3 — ADEN — — Bit 2 Bit 1 Bit 0 Value on POR CCP1IF TMR2IF TMR1IF 0000 FERR OERR RX9D 0000 0000 CCP1IE TMR2IE TMR1IE 0000 BRGH TRMT TX9D 0000 -000 000x 0000 -000 -010 Value on all other Resets 0000 0000 0000 000
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PIC16F627A/628A/648A 12.4.2 USART SYNCHRONOUS MASTER RECEPTION Once Synchronous mode is selected, reception is enabled by setting either enable bit SREN (RCSTA<5>) or enable bit CREN (RCSTA<4>). Data is sampled on the RB1/RX/DT pin on the falling edge of the clock. If enable bit SREN is set, then only a single word is received. If enable bit CREN is set, the reception is continuous until CREN is cleared. If both bits are set then CREN takes precedence.
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PIC16F627A/628A/648A FIGURE 12-14: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) Q2 Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q1Q2Q3Q4Q1Q2Q3Q4 Q1Q2Q3Q4Q1Q2Q3 Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q1Q2Q3Q4 RB1/RX/DT PIN BIT0 BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 BIT7 RB2/TX/CK PIN WRITE TO BIT SREN SREN BIT CREN BIT ‘0’ ‘0’ RCIF BIT (INTERRUPT) READ RXREG Note: 12.5 Timing diagram demonstrates Sync Master Mode with bit SREN = ‘1’ and bit BRG = ‘0’.
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PIC16F627A/628A/648A 12.5.2 USART SYNCHRONOUS SLAVE RECEPTION 2. The operation of the Synchronous Master and Mlave modes is identical except in the case of the Sleep mode. Also, bit SREN is a don't care in Slave mode. If receive is enabled, by setting bit CREN, prior to the SLEEP instruction, then a word may be received during Sleep.
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PIC16F627A/628A/648A NOTES: DS40044B-page 88 Preliminary  2004 Microchip Technology Inc.
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PIC16F627A/628A/648A 13.0 DATA EEPROM MEMORY The EEPROM data memory is readable and writable during normal operation (full VDD range). This memory is not directly mapped in the register file space. Instead it is indirectly addressed through the Special Function Registers (SFRs). There are four SFRs used to read and write this memory. These registers are: The EEPROM data memory allows byte read and write. A byte write automatically erases the location and writes the new data (erase before write).
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PIC16F627A/628A/648A 13.1 EEADR Control bits RD and WR initiate read and write, respectively. These bits cannot be cleared, only set, in software. They are cleared in hardware at completion of the read or write operation. The inability to clear the WR bit in software prevents the accidental, premature termination of a write operation. The PIC16F648A EEADR register addresses 256 bytes of data EEPROM. All eight bits in the register (EEADR<7:0>) are required.
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PIC16F627A/628A/648A 13.3 READING THE EEPROM DATA MEMORY To read a data memory location, the user must write the address to the EEADR register and then set control bit RD (EECON1<0>). The data is available, in the very next cycle, in the EEDATA register; therefore it can be read in the next instruction. EEDATA will hold this value until another read or until it is written to by the user (during a write operation).
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PIC16F627A/628A/648A 13.7 Using the Data EEPROM For this reason, variables that change infrequently (such as constants, IDs, calibration, etc.) should be stored in Flash program memory. The data EEPROM is a high endurance, byte addressable array that has been optimized for the storage of frequently changing information (e.g., program variables or other data that are updated often). Frequently changing values will typically be updated more often than specification D124.
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PIC16F627A/628A/648A 14.0 SPECIAL FEATURES OF THE CPU Special circuits to deal with the needs of real-time applications are what sets a microcontroller apart from other processors. The PIC16F627A/628A/648A family has a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving Operating modes and offer code protection. These are: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12.
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PIC16F627A/628A/648A REGISTER 14-1: CP — CONFIGURATION WORD — — — CPD LVP BOREN MCLRE FOSC2 PWRTE WDTE F0SC1 bit 13 bit 0 bit 13: CP: Flash Program Memory Code Protection bit(2) (PIC16F648A) 1 = Code protection off 0 = 0000h to 0FFFh code protected (PIC16F628A) 1 = Code protection off 0 = 0000h to 07FFh code protected (PIC16F627A) 1 = Code protection off 0 = 0000h to 03FFh code protected bit 12-9: Unimplemented: Read as ‘0’ bit 8: CPD: Data Code Protection bit(3) 1 = Data memory code pro
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PIC16F627A/628A/648A 14.2 TABLE 14-1: Oscillator Configurations 14.2.1 OSCILLATOR TYPES The PIC16F627A/628A/648A can be operated in eight different oscillator options. The user can program three configuration bits (FOSC2 through FOSC0) to select one of these eight modes: • • • • • • LP Low Power Crystal XT Crystal/Resonator HS High Speed Crystal/Resonator RC External Resistor/Capacitor (2 modes) INTOSC Internal Precision Oscillator (2 modes) EC External Clock In 14.2.
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PIC16F627A/628A/648A FIGURE 14-2: EXTERNAL PARALLEL RESONANT CRYSTAL OSCILLATOR CIRCUIT FIGURE 14-4: EXTERNAL CLOCK INPUT OPERATION (EC, HS, XT OR LP OSC CONFIGURATION) +5V TO OTHER DEVICES Clock From ext. system 10K 4.7K 74AS04 PIC16F627A/628A/648A 10K 14.2.6 C2 Figure 14-3 shows a series resonant oscillator circuit. This circuit is also designed to use the fundamental frequency of the crystal. The inverter performs a 180° phase shift in a series resonant oscillator circuit.
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PIC16F627A/628A/648A 14.2.8 SPECIAL FEATURE: DUAL SPEED OSCILLATOR MODES 14.3 A software programmable dual speed Oscillator mode is provided when the PIC16F627A/628A/648A is configured in the INTOSC Oscillator mode. This feature allows users to dynamically toggle the oscillator speed between 4 MHz and 37 kHz nominal in the INTOSC mode. Applications that require low current power savings, but cannot tolerate putting the part into Sleep, may use this mode.
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PIC16F627A/628A/648A 14.4 14.4.1 Power-on Reset (POR), Power-up Timer (PWRT), Oscillator Start-up Timer (OST) and Brown-out Reset (BOR) The Power-Up Time delay will vary from chip to chip and due to VDD, temperature and process variation. See DC parameters Table 17-7 for details. 14.4.3 POWER-ON RESET (POR) The OST provides a 1024 oscillator cycle (from OSC1 input) delay after the PWRT delay is over. Program execution will not start until the OST time out is complete.
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PIC16F627A/628A/648A 14.4.5 TIME OUT SEQUENCE 14.4.6 On power-up the time out sequence is as follows: First PWRT time out is invoked after POR has expired. Then OST is activated. The total time out will vary based on oscillator configuration and PWRTE bit Status. For example, in RC mode with PWRTE bit set (PWRT disabled), there will be no time out at all. Figure 14-8, Figure 14-9 and Figure 14-10 depict time out sequences. The power control/Status Register, PCON (address 8Eh) has two bits.
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PIC16F627A/628A/648A TABLE 14-5: SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT RESET Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Reset Value on all other Resets(1) 03h, 83h, 103h, 183h STATUS IRP RP1 RPO TO PD Z DC C 0001 1xxx 000q quuu 8Eh PCON — — — — OSCF — POR BOR ---- 1-0x ---- u-uq Legend: Note x = unknown, u = unchanged, - = unimplemented read as ‘0’, q = value depends upon condition. Shaded cells are not used by Brown-out Reset.
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PIC16F627A/628A/648A TABLE 14-7: Register W INITIALIZATION CONDITION FOR REGISTERS Address Power-on Reset • MCLR Reset during normal operation • MCLR Reset during Sleep • WDT Reset • Brown-out Reset (1) • Wake-up from Sleep(7) through interrupt • Wake-up from Sleep(7) through WDT time out — xxxx xxxx uuuu uuuu INDF 00h — — — TMR0 01h, 101h xxxx xxxx uuuu uuuu uuuu uuuu PCL 02h, 82h, 102h, 182h 0000 0000 0000 0000 PC + 1(3) STATUS 03h, 83h, 103h, 183h 0001 1xxx 000q quuu(4) uuuq
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PIC16F627A/628A/648A FIGURE 14-8: TIME OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE VDD MCLR INTERNAL POR Tpwrt PWRT TIME OUT Tost OST TIME OUT INTERNAL RESET TIME OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 FIGURE 14-9: VDD MCLR INTERNAL POR Tpwrt PWRT TIME OUT Tost OST TIME OUT INTERNAL RESET FIGURE 14-10: TIME OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD) VDD MCLR INTERNAL POR Tpwrt PWRT TIME OUT Tost OST TIME OUT INTERNAL RESET DS40044B-page 102 Preliminary  2004
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PIC16F627A/628A/648A FIGURE 14-11: EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP) FIGURE 14-13: EXTERNAL BROWN-OUT PROTECTION CIRCUIT 2 VDD VDD VDD VDD R1 Q1 D R MCLR PIC16F627A/628A/648A R2 R1 40k MCLR PIC16F627A/628A/648A C Note 1: This Brown-out Circuit is less expensive, albeit less accurate. Transistor Q1 turns off when VDD is below a certain level such that: Note 1: External Power-on Reset circuit is required only if VDD power-up slope is too slow.
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PIC16F627A/628A/648A 14.5 Interrupts The PIC16F627A/628A/648A has 10 sources of interrupt: • • • • • • • • • • External Interrupt RB0/INT TMR0 Overflow Interrupt PORTB Change Interrupts (pins RB7:RB4) Comparator Interrupt USART Interrupt TX USART Interrupt RX CCP Interrupt TMR1 Overflow Interrupt TMR2 Match Interrupt Data EEPROM Interrupt The interrupt control register (INTCON) records individual interrupt requests in flag bits. It also has individual and global interrupt enable bits.
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PIC16F627A/628A/648A 14.5.1 RB0/INT INTERRUPT 14.5.3 External interrupt on RB0/INT pin is edge triggered: either rising if INTEDG bit (OPTION<6>) is set, or falling, if INTEDG bit is clear. When a valid edge appears on the RB0/INT pin, the INTF bit (INTCON<1>) is set. This interrupt can be disabled by clearing the INTE control bit (INTCON<4>). The INTF bit must be cleared in software in the interrupt service routine before re-enabling this interrupt.
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PIC16F627A/628A/648A TABLE 14-8: Address SUMMARY OF INTERRUPT REGISTERS Name 0Bh, 8Bh, INTCON 10Bh, 18Bh Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Reset Value on all other Resets(1) GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 EEIF CMIF RCIF TXIF — CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000 8Ch PIE1 EEIE CMIE RCIE TXIE — CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000 Note 1: Other (non Power-up) Resets include MCLR Reset, Brown-ou
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PIC16F627A/628A/648A FIGURE 14-16: WATCHDOG TIMER BLOCK DIAGRAM From TMR0 Clock Source (Figure 6-1) 0 M U 1X Watchdog Timer WDT POSTSCALER/ TMR0 PRESCALER 8 8 to 1 MUX PSA 3 PS<2:0> WDT Enable Bit To TMR0 (Figure 6-1) 0 MUX 1 PSA WDT Time out Note: T0SE, T0CS, PSA, PS0-PS2 are bits in the OPTION register. TABLE 14-9: SUMMARY OF WATCHDOG TIMER REGISTERS Value on POR Reset Value on all other Resets Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 2007h Config.
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PIC16F627A/628A/648A 14.8.1 WAKE-UP FROM SLEEP The device can wake-up from Sleep through one of the following events: 1. 2. 3. External Reset input on MCLR pin Watchdog Timer wake-up (if WDT was enabled) Interrupt from RB0/INT pin, RB Port change, or any Peripheral Interrupt. The first event will cause a device Reset. The two latter events are considered a continuation of program execution. The TO and PD bits in the Status Register can be used to determine the cause of device Reset.
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PIC16F627A/628A/648A 14.11 In-Circuit Serial Programming 14.12 Low Voltage Programming The PIC16F627A/628A/648A microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for power, ground, and the programming voltage. This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product.
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PIC16F627A/628A/648A NOTES: DS40044B-page 110 Preliminary  2004 Microchip Technology Inc.
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PIC16F627A/628A/648A 15.0 INSTRUCTION SET SUMMARY Each PIC16F627A/628A/648A instruction is a 14-bit word divided into an OPCODE which specifies the instruction type and one or more operands which further specify the operation of the instruction. The PIC16F627A/628A/648A instruction set summary in Table 15-2 lists byte-oriented, bit-oriented, and literal and control operations. Table 15-1 shows the opcode field descriptions.
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PIC16F627A/628A/648A TABLE 15-2: PIC16F627A/628A/648A INSTRUCTION SET 14-Bit Opcode Mnemonic, Operands Description Cycles MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f — f, d f, d f, d f, d f, d f, d f, d f — f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive O
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PIC16F627A/628A/648A 15.1 Instruction Descriptions ADDLW Add Literal and W Syntax: [ label ] ADDLW Operands: ANDLW AND Literal with W Syntax: [ label ] ANDLW 0 ≤ k ≤ 255 Operands: 0 ≤ k ≤ 255 Operation: (W) + k → (W) Operation: (W) .AND. (k) → (W) Status Affected: C, DC, Z Status Affected: Z Encoding: 11 Encoding: 11 Description: The contents of the W register are added to the eight bit literal ‘k’ and the result is placed in the W register.
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PIC16F627A/628A/648A BCF Bit Clear f BTFSC Bit Test f, Skip if Clear Syntax: [ label ] BCF Syntax: [ label ] BTFSC f,b Operands: 0 ≤ f ≤ 127 0≤b≤7 Operands: 0 ≤ f ≤ 127 0≤b≤7 Operation: 0 → (f) Operation: skip if (f) = 0 Status Affected: None Status Affected: None Encoding: 01 f,b 00bb bfff Description: Bit ‘b’ in register ‘f’ is cleared.
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PIC16F627A/628A/648A BTFSS Bit Test f, Skip if Set CALL Call Subroutine Syntax: [ label ] BTFSS f,b Syntax: [ label ] CALL k Operands: 0 ≤ f ≤ 127 0≤b<7 Operands: 0 ≤ k ≤ 2047 Operation: Operation: skip if (f) = 1 Status Affected: None (PC)+ 1→ TOS, k → PC<10:0>, (PCLATH<4:3>) → PC<12:11> Encoding: 01 Status Affected: None Description: If bit ‘b’ in register ‘f’ is ‘1’ then the next instruction is skipped.
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PIC16F627A/628A/648A CLRW Clear W COMF Complement f Syntax: [ label ] CLRW Syntax: [ label ] COMF Operands: None Operands: Operation: 00h → (W) 1→Z 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) → (dest) Status Affected: Z Status Affected: Z Encoding: 00 Encoding: 00 Description: W register is cleared. Zero bit (Z) is set. Description: Words: 1 Cycles: 1 The contents of register ‘f’ are complemented. If ‘d’ is 0 the result is stored in W.
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PIC16F627A/628A/648A DECFSZ Decrement f, Skip if 0 GOTO Unconditional Branch Syntax: [ label ] DECFSZ f,d Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ k ≤ 2047 Operation: (f) - 1 → (dest); 0 Operation: k → PC<10:0> PCLATH<4:3> → PC<12:11> Status Affected: None Status Affected: None Encoding: Encoding: 10 00 Description: The contents of register ‘f’ are decremented. If ‘d’ is 0 the result is placed in the W register.
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PIC16F627A/628A/648A INCF Increment f INCFSZ Increment f, Skip if 0 Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) + 1 → (dest) Operation: (f) + 1 → (dest), skip if result = 0 Status Affected: Z Status Affected: None Encoding: 00 Encoding: 00 Description: The contents of register ‘f’ are incremented. If ‘d’ is 0 the result is placed in the W register. If ‘d’ is 1 the result is placed back in register ‘f’.
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PIC16F627A/628A/648A IORLW Inclusive OR Literal with W MOVLW Move Literal to W Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ k ≤ 255 Operation: (W) .OR. k → (W) Operation: k → (W) Status Affected: Z Status Affected: None Encoding: 11 Encoding: 11 Description: The contents of the W register is OR’ed with the eight bit literal ‘k’. The result is placed in the W register. Description: The eight bit literal ‘k’ is loaded into W register.
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PIC16F627A/628A/648A MOVWF Move W to f OPTION Load Option Register Syntax: [ label ] Syntax: [ label ] 0 ≤ f ≤ 127 Operands: None Operands: Operation: (W) → (f) Operation: (W) → OPTION Status Affected: None Status Affected: None Encoding: 00 Encoding: 00 Description: The contents of the W register are loaded in the OPTION register. This instruction is supported for code compatibility with PIC16C5X products.
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PIC16F627A/628A/648A RETLW Return with Literal in W RLF Rotate Left f through Carry Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ k ≤ 255 Operands: Operation: k → (W); TOS → PC 0 ≤ f ≤ 127 d ∈ [0,1] Operation: See description below Status Affected: None Status Affected: C Encoding: 11 Encoding: 00 Description: The W register is loaded with the eight bit literal ‘k’. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction.
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PIC16F627A/628A/648A RRF Rotate Right f through Carry SUBLW Subtract W from Literal Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ k ≤ 255 Operation: k - (W) → (W) Operation: See description below C, DC, Z Status Affected: C Status Affected: Encoding: 00 Encoding: 11 Description: The contents of register ‘f’ are rotated one bit to the right through the Carry Flag. If ‘d’ is 0 the result is placed in the W register.
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PIC16F627A/628A/648A SUBWF Subtract W from f SWAPF Swap Nibbles in f Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) - (W) → (dest) Operation: Status Affected: C, DC, Z (f<3:0>) → (dest<7:4>), (f<7:4>) → (dest<3:0>) Status Affected: None Encoding: 00 Encoding: 00 Description: Subtract (2’s complement method) W register from register ‘f’. If ‘d’ is 0 the result is stored in the W register.
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PIC16F627A/628A/648A XORLW Exclusive OR Literal with W XORWF Exclusive OR W with f Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (W) .XOR. (f) → (dest) Status Affected: Z Encoding: 00 Description: Exclusive OR the contents of the W register with register ‘f’. If ‘d’ is 0 the result is stored in the W register. If ‘d’ is 1 the result is stored back in register ‘f’. Words: 1 Cycles: 1 Example XORWF XORLW k Operation: (W) .XOR.
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PIC16F627A/628A/648A 16.0 DEVELOPMENT SUPPORT 16.
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PIC16F627A/628A/648A 16.3 MPLAB C17 and MPLAB C18 C Compilers 16.6 The MPLAB C17 and MPLAB C18 Code Development Systems are complete ANSI C compilers for Microchip’s PIC17CXXX and PIC18CXXX family of microcontrollers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 16.
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PIC16F627A/628A/648A 16.9 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator 16.11 MPLAB ICD 2 In-Circuit Debugger The MPLAB ICE 2000 universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PICmicro microcontrollers.
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PIC16F627A/628A/648A 16.14 PICSTART Plus Development Programmer 16.17 PICDEM 2 Plus Demonstration Board The PICSTART Plus development programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus development programmer supports most PICmicro devices up to 40 pins.
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PIC16F627A/628A/648A 16.20 PICDEM 17 Demonstration Board The PICDEM 17 demonstration board is an evaluation board that demonstrates the capabilities of several Microchip microcontrollers, including PIC17C752, PIC17C756A, PIC17C762 and PIC17C766. A programmed sample is included. The PRO MATE II device programmer, or the PICSTART Plus development programmer, can be used to reprogram the device for user tailored application development.
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PIC16F627A/628A/648A NOTES: DS40044B-page 130 Preliminary  2004 Microchip Technology Inc.
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PIC16F627A/628A/648A 17.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings(†) Ambient temperature under bias................................................................................................................. -40 to +125°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on VDD with respect to VSS ..........................................................................
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PIC16F627A/628A/648A PIC16F627A/628A/648A VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C FIGURE 17-1: 6.0 5.5 5.0 VDD (VOLTS) 4.5 4.0 3.5 3.0 2.5 4 0 10 20 25 FREQUENCY (MHz) Note: The shaded region indicates the permissible combinations of voltage and frequency. PIC16LF627A/628A/648A VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +85°C FIGURE 17-2: 6.0 5.5 5.0 4.5 VDD (VOLTS) 4.0 3.5 3.0 2.5 2.
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PIC16F627A/628A/648A 17.1 DC Characteristics: PIC16F627A/628A/648A (Industrial, Extended) PIC16LF627A/628A/648A (Industrial) PIC16LF627A/628A/648A (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ Ta ≤ +85°C for industrial PIC16F627A/628A/648A (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ Ta ≤ +85°C for industrial and -40°C ≤ Ta ≤ +125°C for extended Param No.
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PIC16F627A/628A/648A 17.2 DC Characteristics: PIC16F627A/628A/648A (Industrial) PIC16LF627A/628A/648A (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ Ta ≤ +85°C for industrial Param No. LF and F Device Characteristics Min† Typ Max Conditions Units VDD Note Supply Voltage (VDD) D001 LF 2.0 — 5.5 V — LF/F 3.0 — 5.5 V — — 0.1 0.80 µA 2.0 — 0.1 0.85 µA 3.0 — 0.2 2.7 µA 5.0 — 1 2.0 µA 2.0 — 2 3.4 µA 3.0 — 9 17.
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PIC16F627A/628A/648A 17.3 DC Characteristics: PIC16F627A/628A/648A (Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ Ta ≤ +125°C for extended Param No. Device Characteristics Min† Typ Max Conditions Units VDD Note Supply Voltage (VDD) D001 — 3.0 — 5.5 V — Power-down Base Current (IPD) D020E — — 0.1 TBD µA 3.0 — 0.2 TBD µA 5.0 WDT, BOR, Comparators, VREF, and T1OSC: disabled — 2 TBD µA 3.
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PIC16F627A/628A/648A 17.4 DC Characteristics: PIC16F627A/628A/648A (Industrial, Extended) PIC16LF627A/628A/648A (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial and -40°C ≤ TA ≤ +125°C for extended Operating voltage VDD range as described in DC spec Table 17-2 and Table 17-3 DC CHARACTERISTICS Param. No.
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PIC16F627A/628A/648A TABLE 17-1: DC Characteristics: PIC16F627A/628A/648A (Industrial, Extended) PIC16LF627A/628A/648A (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial and -40°C ≤ TA ≤ +125°C for extended Operating voltage VDD range as described in DC spec Table 17-2 and Table 17-3 DC Characteristics Parameter Sym No.
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PIC16F627A/628A/648A TABLE 17-2: COMPARATOR SPECIFICATIONS Operating Conditions: 2.0V < VDD <5.5V, -40°C < TA < +125°C, unless otherwise stated. Param No. Characteristics Sym Min Typ Max Units D300 Input Offset Voltage VIOFF — ±5.0 ±10 mV D301 Input Common Mode Voltage VICM 0 — VDD - 1.
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PIC16F627A/628A/648A 17.5 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2.
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PIC16F627A/628A/648A 17.6 Timing Diagrams and Specifications FIGURE 17-4: EXTERNAL CLOCK TIMING Q4 Q1 Q3 Q2 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT TABLE 17-4: Parameter No. EXTERNAL CLOCK TIMING REQUIREMENTS Sym Fosc Characteristic External CLKIN Frequency(1) Oscillator Frequency(1) 1 Tosc External CLKIN Period(1) Oscillator Period(1) 2 3 4 * Tcy TosL, TosH RC Min Typ† Max DC — 4 DC DC — 0.
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PIC16F627A/628A/648A TABLE 17-5: PRECISION INTERNAL OSCILLATOR PARAMETERS Parameter No. Sym F10 FIOSC ∆IOSC F13 F14 Characteristic Min Max Units Oscillator Center frequency — 4 — MHz Oscillator Stability (jitter) — — — — ±1 ±2 % % — — ±5 % — — — 6 4 3 TBD TBD TBD µs µs µs TIOSCST Oscillator Wake-up from Sleep start-up time FIGURE 17-5: Typ Conditions VDD = 3.5 V, 25°C 2.0 V ≤ VDD ≤ 5.5V 0°C ≤ TA ≤ +85°C 2.0 V ≤ VDD ≤ 5.
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PIC16F627A/628A/648A TABLE 17-6: Parameter No.
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PIC16F627A/628A/648A FIGURE 17-7: BROWN-OUT DETECT TIMING VBOR VDD 35 TABLE 17-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER REQUIREMENTS Parameter No.
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PIC16F627A/628A/648A TABLE 17-8: Param No. Sym 40 Tt0H 41 42 45 46 47 48 * TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Characteristic Min Typ† Max Units Conditions T0CKI High Pulse Width No Prescaler 0.5TCY + 20* — — ns With Prescaler 10* — — ns Tt0L T0CKI Low Pulse Width No Prescaler 0.5TCY + 20* — — ns With Prescaler 10* — — ns Tt0P T0CKI Period Greater of: — — ns N = prescale TCY + 40* value (2, 4, ..., N 256) Tt1H T1CKI High Synchronous, No Prescaler 0.
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PIC16F627A/628A/648A TABLE 17-9: CAPTURE/COMPARE/PWM REQUIREMENTS Param Sym No. 50 Characteristic TccL CCP input low time Min No Prescaler 51 TccH CCP input high time — — ns 10* — — ns PIC16LF62X 20* — — ns 0.5TCY + 20* — — ns PIC16F62X 10* — — ns PIC16LF62X 20* — — ns 3TCY + 40* N — — ns PIC16F62X 10 25* ns PIC16LF62X 25 45* ns No Prescaler With Prescaler 52 TccP CCP input period 53 TccR CCP output rise time 54 0.
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PIC16F627A/628A/648A NOTES: DS40044B-page 146 Preliminary  2004 Microchip Technology Inc.
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PIC16F627A/628A/648A 18.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES Not Available at this time.  2004 Microchip Technology Inc.
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PIC16F627A/628A/648A NOTES: DS40044B-page 148 Preliminary  2004 Microchip Technology Inc.
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PIC16F627A/628A/648A 19.0 PACKAGING INFORMATION 19.1 Package Marking Information 18-LEAD PDIP (.300") XXXXXXXXXXXXXX XXXXXXXXXXXXXX EXAMPLE PIC16F627A-I/P YYWWNNN 18-LEAD SOIC (.300") XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN EXAMPLE PIC16F628A -E/SO 0210017 20-LEAD SSOP EXAMPLE XXXXXXXXXXX XXXXXXXXXXX YYWWNNN PIC16F648A -I/SS 0210017 28-LEAD QFN EXAMPLE XXXXXXXX XXXXXXXX YYWWNNN 16F628A -I/ML 0210017 Legend: XX...
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PIC16F627A/628A/648A 18-Lead Plastic Dual In-line (P) – 300 mil (PDIP) E1 D 2 n α 1 E A2 A L c A1 B1 β p B eB Units Dimension Limits n p MIN INCHES* NOM 18 .100 .155 .130 MAX MILLIMETERS NOM 18 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 22.61 22.80 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MIN Number of Pins Pitch Top to Seating Plane A .140 .170 Molded Package Thickness A2 .115 .145 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .300 .313 .
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PIC16F627A/628A/648A 18-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC) E p E1 D 2 B n 1 h α 45° c A2 A φ β L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom A A2 A1 E E1 D h L φ c B α β MIN .093 .088 .004 .394 .291 .446 .010 .016 0 .009 .014 0 0 A1 INCHES* NOM 18 .050 .
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PIC16F627A/628A/648A 20-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP) E E1 p D B 2 1 n α c A2 A φ L A1 β Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Foot Length Lead Thickness Foot Angle Lead Width Mold Draft Angle Top Mold Draft Angle Bottom A A2 A1 E E1 D L c φ B α β MIN .068 .064 .002 .299 .201 .278 .022 .004 0 .010 0 0 INCHES* NOM 20 .026 .073 .068 .006 .309 .
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PIC16F627A/628A/648A 28-Lead Plastic Quad Flat No Lead Package (ML) 6x6 mm Body (QFN) EXPOSED METAL PADS E E1 Q D1 D D2 p 2 1 B n R E2 CH x 45 L TOP VIEW BOTTOM VIEW α A2 A A1 A3 Units Dimension Limits Number of Pins INCHES MIN MILLIMETERS* NOM n MIN MAX MAX NOM 28 28 Pitch p Overall Height A .033 .039 0.85 1.00 Molded Package Thickness A2 .026 .031 0.65 0.80 Standoff A1 .0004 .002 0.01 0.05 Base Thickness A3 .008 REF. 0.20 REF. 6.00 BSC .000 E .
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PIC16F627A/628A/648A NOTES: DS40044B-page 154 Preliminary  2004 Microchip Technology Inc.
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PIC16F627A/628A/648A APPENDIX A: DATA SHEET REVISION HISTORY APPENDIX B: DEVICE DIFFERENCES The differences between the PIC16F627A/628A/648A devices listed in this data sheet are shown in Table B-1. Revision A This is a new data sheet.
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PIC16F627A/628A/648A APPENDIX C: DEVICE MIGRATIONS This section describes the functional and electrical specification differences when migrating between functionally similar devices. (such as from a PIC16F627 to a PIC16F627A). C.1 1. 2. 3. 4. 5. 6. 7. PIC16F627/628 to a PIC16F627A/628A ER mode is now RC mode. Code Protection for the Program Memory has changed from Code Protect sections of memory to Code Protect of the whole memory.
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PIC16F627A/628A/648A APPENDIX E: DEVELOPMENT TOOL VERSION REQUIREMENTS This lists the minimum requirements (software/ firmware) of the specified development tool to support the devices listed in this data sheet.
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PIC16F627A/628A/648A NOTES: DS40044B-page 158 Preliminary  2004 Microchip Technology Inc.
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PIC16F627A/628A/648A ON-LINE SUPPORT Microchip provides on-line support on the Microchip World Wide Web site. The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape® or Microsoft® Internet Explorer. Files are also available for FTP download from our FTP site.
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PIC16F627A/628A/648A READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
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PIC16F627A/628A/648A INDEX A A/D Special Event Trigger (CCP)....................................... 57 Absolute Maximum Ratings .............................................. 131 ADDLW Instruction ........................................................... 113 ADDWF Instruction ........................................................... 113 ANDLW Instruction ........................................................... 113 ANDWF Instruction ...........................................................
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PIC16F627A/628A/648A E EECON1 register ................................................................ 90 EECON2 register ................................................................ 90 Errata .................................................................................... 3 Evaluation and Programming Tools .................................. 129 External Crystal Oscillator Circuit........................................ 95 G General-Purpose Register File............................................
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PIC16F627A/628A/648A Power Control/Status Register (PCON) .............................. 99 Power-Down Mode (SLEEP) ............................................ 107 Power-On Reset (POR) ...................................................... 98 Power-up Timer (PWRT) .................................................... 98 PR2 Register................................................................. 52, 58 PRO MATE II Universal Device Programmer ................... 127 Program Memory Organization .............
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PIC16F627A/628A/648A Sampling ......................................................... 72, 73, 74 Synchronous Master Mode ......................................... 83 Synchronous Master Reception .................................. 85 Synchronous Master Transmission............................. 83 Synchronous Slave Mode ........................................... 86 Synchronous Slave Reception .................................... 87 Synchronous Slave Transmit ......................................
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PIC16F627A/628A/648A PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. -X /XX XXX Device Temperature Range Package Pattern Examples: a) PIC16F627A - E/P 301 = Extended Temp., PDIP package, 20 MHz, normal VDD limits, QTP pattern #301. b) Device PIC16F627A/628A/648A:Standard VDD range 3.0V to 5.5V PIC16F627A/628A/648ATVDD range 3.0V to 5.5V (Tape and Reel) PIC16LF627A/628A/648A:VDD range 2.0V to 5.
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WORLDWIDE SALES AND SERVICE AMERICAS China - Beijing Korea Corporate Office Unit 706B Wan Tai Bei Hai Bldg. No. 6 Chaoyangmen Bei Str. Beijing, 100027, China Tel: 86-10-85282100 Fax: 86-10-85282104 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea 135-882 Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 China - Chengdu 200 Middle Road #07-02 Prime Centre Singapore, 188980 Tel: 65-6334-8870 Fax: 65-6334-8850 2355 West Chandler Blvd.