User`s manual

PCI-FRM01 User’s Manual (Rev 1.1)
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PCI Target
/ Master
PCI BUS
Local Bus
Address
Data(Mem,I/O)
Reserved
(0x00 ? 0x5F)
Reserved
(0x70 ? 0xAF)
UART
(0x60)
Camera Link(LVDS)
(0xC0)
Interrupt controller
DIO
(0xD0)
Ext. Address, Data, Control
Local BUS
Interrupt
Controller
(0xb0)
INT sources in Chip
IO Decoder
MEM Decoder
To each IO
Module
PCI-FRM01 INTERNAL BLOCK - FPGA
DPRAM
From Ext.
CLOCK syn.
MEM Decoder
BUS Mux
Reserved
(0xE0 ? 0xFF)
[Figure 2-1. Functional Block Diagram]
The FPGA Core Logic programming is performed via the JTAG interface. The logic program of the FPGA is
saved in an EPLD. It is located on the board and loaded at the power-up time.
[ Features of the PCI-FRM01 board]
 32-bit PCI-Bus 33MHz Interface, Plug and Play
 PCI Bus Master Operation
 PCI 5V and 3.3V compatible operation.
 Receiving 14-bit Frame data
 UART communication (8 bit data, 1 start, 1 stop, No parity, 9600bps)
 16-bit Digital Input and 8-bit Digital Output
 Windows 2000 SP4 or Windows XP SP1 above
 Convenient Windows Application Programming Interface(DLL)