Danville Signal Processing, Inc. dspstak™ 21262sx User Manual Version 1.
Danville Signal Processing, Inc. dspstak™ 21262sx User Manual Copyright © 2004 Danville Signal Processing, Inc. All rights reserved. Printed in the USA. Under the copyright laws, this manual may not be reproduced in any form without prior written permission from Danville Signal Processing, Inc. Danville Signal Processing, Inc. strives to deliver the best product to our customers. As part of this goal, we are constantly trying to improve our products. Danville Signal Processing, Inc.
Table of Contents Overview ..........................................................................5 Introducing dspstak™.............................................................................5 dspstak™ 21262sx .................................................................................5 Introduction...........................................................................................6 Hardware Description......................................................7 Power Supply ...............
USB & PLD Registers ......................................................28 Addressing USB & PLD Registers ..........................................................28 PLD Output & USB Status Registers .....................................................28 Memory Map.......................................................................................29 USB Port..............................................................................................29 PLD Output Registers............................
Overview DSP-based embedded applications often take the form of a digital signal processing engine coupled with a specialized data conversion and signal conditioning front end. The front end electronics and the DSP are almost always connected via high speed serial ports and the general purpose I/O ports of the DSP. In most cases, once the local memory and peripheral interfacing needs of the DSP are fulfilled, the DSP’s data and address busses are no longer needed.
Intended Audience The dspstak 21262sx is intended for DSP systems integrators, designers and programmers who may wish to integrate a dspstak into their products. This manual is primarily aimed at users who have a working knowledge of microcomputer technology and DSP related design. We assume that you are familiar with the Analog Devices ADSP-21262 SHARC DSP. Introduction The dspstak™ 21262sx is a high performance digital signal processing engine based on the Analog Devices ADSP-21262 SHARC DSP.
• • • Analog Devices ADSP-2126x SHARC® DSP Peripherals Manual Analog Devices ADSP-21262S Product Data Sheet Cypress Semiconductor CyberClocks™ Our website (www.danvillesignal.com) has downloads and links to other supplementary tools and documents. Hardware Description The dspstak 21262sx includes all dspstak DSP Engine standard features.
Volt Digital) and Vd+3.3 (3.3V Digital) are created and made available to the I/O Modules via the Interconnect Port. The DSP Core voltage, Vd+1.2 is also created via a switching power supply. The dspstak 21262sx DSP Engine does not use Va+, Va+5 or Va-. These supplies are available to I/O Modules. If the I/O Module does not need a negative supply, you can power the dspstak 21262sx with only a positive DC power supply. The recommended input voltages are 9 VAC or 9 to 15VDC.
When the dspstak 21262sx is programmed using the RS-232 interface, only RD & TD are used. DTR, DSR & DCD are simply connected together and ignored by the dspstak. The dspstak 21262sx supports standard bauds of 9600, 19.2k, 38.4k, 57.6k, 115.2k and 230.4k. The expected protocol is No parity, 8 data bits, 1 stop bit, (N:8:1). USB Interface The USB interface is another way that programs may be uploaded to the dspstak.
JTAG Emulation Port The dspstak 21262sx has a right angle JTAG connector (JH3) mounted on the lower edge of the pcb assembly. This connector is assessable even when a dspstak I/O Module is positioned above the dspstak 21262sx. Danville JTAG connectors are smaller than the standard ADI recommended JTAG header. The Danville JTAG connector is a male 16 pin, 2mm dual row header. Each pin directly corresponds to the same pins on the Analog Devices header. The remaining pins (15&16) are assigned to Vd+3.3.
Module, then you may map the DAI any way you want on the Interconnect Port. We expect that future dspstak DSP Engines will also have DAI mapped connections routed to the same connections on the Interconnect Port. Here are the DAI to Interconnect Port Mappings: Row A&C B Name 1 2 3 4 5 * * * * * * * * * * AGND Va+ VaVa+5 AGND Analog Ground Unregulated Positive Analog Supply Unregulated Negative Analog Supply Regulated Analog +5.0 Volt Supply Analog Ground 6 7 8 * * * * * * Vd+5 Vd+3.
Row A&C 20 20 21 21 22 22 23 23 24 24 * 25 25 26 26 27 27 28 28 29 29 30 30 31 31 32 32 B * * * * * * * * * * * * * * * * * * * * * * * * * Name RFS0 TFS0 RCLK0 TCLK0 #RESET0 GND DTB0 DRB0 GND Vd+3.3 Vd+3.3 GND DRA1 DTA1 GND MCLK1 RFS1 TFS1 RCLK1 TCLK1 #RESET1 GND DTB1 DRB1 GND Vd+3.
Parallel Port The Parallel Port is connected to two major components, the USB Port and a PLD that is used to create and manage much of the dspstak’s I/O ports. In addition, the Parallel Port is brought out to a 30 pin 2mm female dual row header (JH2). You can use JH2 to expand to your own Parallel Port devices provided you consider a few simple points.
SPI Port The SPI is used as a general purpose control bus on the dspstak 21262sx. It is connected to two onboard components, a serial flash memory and the Peripheral Microcontroller. It is also available on the Interconnect Port to control data converters and provide general purpose I/O expansion. Like all other dspstak DSP Engines, the DSP is always the master. The flash memory is selected via Flag 0 of the ADSP-21262.
Programming the dspstak™ 21262sx The dspstak 21262sx can be programmed in a variety of ways. In most cases, programs are uploaded via either the USB port or RS-232 port into the on-board serial flash memory. You may also load and execute programs through the JTAG port by using an emulator. Programming Modes The dspstak 21262sx has eight different programming modes that are assigned via jumper on the Configuration Header (JH5).
Configuration Jumpers JH5 is also used to select the boot configuration and clock configuration of the ADSP-21262. The connections are made directly to the ADSP-21262 BOOTCFG1-0 & CLKCFG1-0 Pins. In most cases, the factory default settings will not need to be changed.
Clock reprogramming is managed entirely by the Peripheral Microcontroller via its RS-232 port. It is not dependent on the ADSP-21262 DSP. The Peripheral Microcontroller also gets its clock from the CY22393 so steps have been taken to protect this clock from inadvertent modification. The following table describes the CY22393 mapping to the dspstak 21262sx.
Uploading Programs – Mode 6 The dspstak 21262sx uses a 2Mbit SPI serial flash memory device to bootload the ADSP-21262. Assuming that the boot mode selection is set for SPI Master Boot (see Configuration Jumpers), the ADSP-21262 will boot from the SPI flash memory after reset is deasserted. This boot capability is very useful in the ADSP-21262 except that there is no native support in the DSP to program the flash memory.
Here are the basic steps to uploading programs: • Configure the dspstak 21262sx to operate in Mode 6. • Connect to an ASCII Terminal Program via RS-232 or USB. USB is faster. o If RS-232 is used, a 9 pin to 9 pin cable with no twists is appropriate on PC compatible computers. The default serial configuration is 19.2K, N, 8, 1. Handshaking lines are ignored. There is a command to change the baud rate to higher speeds. If you don’t know the current baud rate, you can reset the baud via Mode 7 to 19.2K.
• After the program is uploaded, a checksum is calculated and you have the opportunity to enter a description of the program. The program description is an ASCII string that you can use to identify your program. It does not impact the function of the DSP module in any way, but can be a helpful way to track program revisions. A typical program description might be "Filter version 1.00.” The size of the program is also calculated. • Type Q to quit Command Mode and the application program will boot.
Peripheral Microcontroller API The Peripheral Microcontroller communicates via the SPI bus using a 3 byte packet structure. Flag 1 serves as the SPI slave select line. The SPI bus is bi-directional. Commands are always initiated by the DSP. The Peripheral Microcontroller only responds.
System Commands Status Description: Peripheral Microcontroller Status Command: Any Status is automatically updated each time a packet is transmitted by the DSP. It is reported in Byte 1 in the next packet. This means that the status reported in the very first packet may not be valid. Status is only valid up to the point of the completion of the previous command. So, if the last command was 2 weeks ago, the status bits will be two weeks old.
PM_Cmd_VERSION Description: Command: Data: Response: Returns the firmware version of the Peripheral Microcontroller 0x03 Don’t Care 0x00 The current version is 0x00, but future versions will increment this number. This allows you to determine what functions this particular Peripheral Microcontroller implements in the event that there are changes in a later version.
PM_Cmd_RESET Description: Command: Data: Response: Reset the dspstak 21262sx 0x0A 0xC4 Don’t Care This is a software reset that acts just like a hardware reset. PM_Cmd_MODE Description: Command: Data: Response: Return Mode Jumper Settings 0x0B Don’t Care See Below Returns the mode setting selected by M2, M1, M0 in the lowest three bits of the response. Modes 0 through 3 are User Modes.
PM_Cmd_RESYNC Description: Command: Data: Byte 3 (DSP): Response: Resync the Peripheral Microcontroller 0x0F 0x0F 0x0F 0x00 This command is used in the event that packet order is somehow misaligned. After this command is executed, the Peripheral Controller will expect the next byte to be Byte 1. Com Port Commands PM_Cmd_COM_WR Description: Command: Data: Response: Write to the Com Port. 0x01 Byte to transmit 0x00 This command puts a byte on the transmit FIFO.
PM_Cmd_COM_BAUD Description: Command: Data: Response: Sets the Baud rate 0x04 See Below 0x00 Baud = (1.152 * 10^6 ) / (DATA + 1) Typical Values: 230.4K 115.2K 38.4K 19.2K 9600 0x04 0x09 0x1F 0x3D 0x79 PM_Cmd_COM_RESET Description: Command: Data: Response: Resets the Com Port 0x08 Don’t Care 0x00 This command resets the UART, flushes the Transmit and Receive FIFOs and clears the UART Overrun Status bit.
PM_Cmd_EE_WREN Description: Command: Data: Response: Enables Writes to the EE Memory 0x09 0x42 (Enable), All other values (Disable) 0x00 This command allows the EE memory to be written. You should disable writes after you are done writing the EE Memory. EE_WREN is always disabled after a system reset. PM_Cmd_EE_WR Description: Command: Data: Response: Write EE at current EE Address 0x06 EE Data 0x00 This command is only valid if the EE_WREN has been enabled.
USB & PLD Registers The dspstak 21262sx uses a PLD for I/O expansion. It is connected to the DSP’s Parallel Port. The USB port is also connected to the Parallel Port. It uses the PLD for part of its internal interface. The Parallel Port on the ADSP-21262 has 16 multiplexed address and data lines and three control lines, ALE, RD & WR. It can be configured as either an 8 bit bus with 24 address lines or a 16 bit bus with 16 address lines. ALE is used as an address latch enable to demultiplex the bus.
Memory Map Name Addr Dir Bits Used Description USB_DATA USB_STATUS PLD_DAI_SPI_SELECT PLD_OUT0 PLD_OUT1 PLD_SPI_SELECT PLD_WD 0x8000 0x9000 0xA000 0xB000 0xC000 0xD000 0xE000 R/W R W W W W W D7-D0 D15-D12 D15-D12 D15-D12 D15-D12 D15-D12 None USB Data Bus USB Status Selects between IO & SPISSs LED3 – LED0 LED4 & #RESETs SPI Mask Watchdog Strobe User Space (JH2) <0x8000 User Space (JH2) 0xF000 This space is available to external devices This space is available to external devices USB Port The U
USB Status Bits Address: 0x9000 PWREN: TXE: RXF: D14 D13 D12 0 – USB Port is enumerated 0 – Transmit FIFO can accept a byte 0 – Receive Buffer has a byte ready All other bits are Don’t Care. Reading the USB Port • • Read the USB Status Register. If RXF is low (and assuming PWREN is low), you may read the USB Data. Read the USB Data Register. This seems pretty straightforward until you learn the “gotcha.
PLD Output Registers PLD_DAI_SPI_SELECT Description: Selects I/O or SPI SS mapping Destination: Interconnect Port Address: 0xA000 IO7/#SPISS3: IO6/#SPISS2: IO5/#SPISS1: D15 D14 D13 0 – IO7 0 – IO6 0 – IO5 1 – #SPISS3 1 – #SPISS2 1 – #SPISS1 All other bits are Don’t Care. This register determines whether the IO Pins on the Interconnect Port are bidirectional GP I/O Pins or SPI slave select lines.
PLD_OUT1 Description: 3.3V Digital Output Destination: Interconnect Port Address: 0xC000 #RESET: #RESET1 #RESET0: LED4: D15 D14 D13 D12 0 – Output Low 0 – Output Low 0 – Output Low 0 – Output Low All other bits are Don’t Care. This register causes the LED4 and the RESET lines on the Interconnect Port to be driven. There are no series limiting resistors in these lines. PLD_SPI_SELECT Description: 3.
PLD_WD Description: 3.3V Digital Output Destination: Peripheral Microcontroller Address: 0xE000 All data bits are Don’t Care. A write to this register causes the Watchdog input on the Peripheral Microcontroller to toggle. If the Watchdog Timer is enabled, you must write to this register before the Watchdog Timer can overflow or the system will reset. Software The Distribution CD includes software examples that demonstrate many of the features of the dspstak 21262sx.
Product Warranty Danville Signal Processing, Inc. products carry the following warranty: Danville Signal Processing products are warranted against defects in materials and workmanship. If Danville Signal Processing receives notice of such defects during the warranty period, Danville Signal Processing shall, at its option, either repair or replace hardware products, which prove to be defective.
