User`s manual

22 • Part I: PC2-CamLink Board PC2-CamLink User's Manual
Data Port
Sequencer
ILUT
Window
YCrCb
Engine
y
y
y
Camera
Camera
Control
y
y
y
y
y
Supports EXSYNC and PRIN camera control signals
2 Opto or 2 LVDS frame trigger inputs
Shaft-Encoder LVDS inputs
Serial Port
y
y
1 Base CameraLink, areascan or line scan
1 or 2 channel(s)
8 to 16-bit per pixel
1 LUT for each CameraLink port
Generator
Creates region of interest (ROI)
Optionally converts to 16-bit padded YCrCb for display
y
Scatter/gather engine that grabs into host logical memory
minimizing CPU usage
y
32-bit/33 MHz high-speed PCI interface (5V and 3.3V)
PCI
Controller
To PCI bus
y
y
1 or 2 channel(s)
Optional truncation to 8-bit
Figure 1: Flow Diagram