Service manual

CP-850/F Service Manual
-26-
4.3.1 BLOCK DIAGRAM OF THE DDP 3315C
Clock
Generator
Input
Interface
Upcon-
Version/
Scaling
Matrix /
PFG /
NCE
Video
DAC
Analog
RGB
Switch
Tube
Control
H & V
H / V
V
V
H
HH
EW
V
H
EW
V
dynamic
focus
Sawtooth /
Parabola
Generation
H-Drive
Generation
Display-
Freq.
Doubling
Sync
Pro-
cessing
EHT
I
2
C
Interface
General
purpose
PWM
SDA
SCL
LLC
27/32/
54 MHz
Y /
656 YCrCb
CrCb
4:2:2 /
4:1:1
PWM 1/2 2H / 2V
(1H / 1V)
FIFO
Controlling
HFLB
DFVBL
PWMV
VPROT
HSAFETY
HOUT
E/W
VERT
VERT+
Output
Input
Sense
Input
Security
Unit
Picture
Improve-
ment
Y
Cb
Cr
Y
Cb
Cr
Y
Cb
Cr
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
Pr
Y
Pb
FBL
R G B FBL
SVM
SVM
analog
RGB-
Matrix
4.3 DDP 3315C - DISPLAY AND DEFLECTION PROCESSOR
The DDP 3315C is a mixed-signal single-chip digital display and deflection processor, designed
for high-quality backend applications in double scan and HDTV TV sets with 4:3 or 16:9 picture
tubes. The interfaces qualify the IC to be combined with state of the art digital scan rate
converters, as well as analog HDTV sources. The DDP 3315C contains the entire digital video
component, deflection processing, and all analog interfaces to display the picture on a CRT.