Hardware reference guide

DSN-2100 Hardware Reference Guide 27
Table A-1. xStack Storage Array DIMM Specifications
Requirement Description
PC2700/DDR333 speed SDRAMs must be JEDEC compliant and DDR333 capable, with a CAS latency of 2.5.
PC2100/DDR400 speed DIMMs can be used if they support a 2.5 CAS latency when
operating at DDR333 speed.
ECC DIMMs must be organized as x72 bits wide, allowing support for ECC.
X8 RAMs DIMMs must use 8-bit wide DRAMs that can support data mask (DM) signals. DIMMs that
use 4-bit-wide DRAMs do not provide DM signals and cannot be used.
Registered DIMMs must be registered as per the JEDEC specification for registered DIMMs.
Buffered DIMMs must be buffered as per the JEDEC specification for buffered DIMMs.
Organization Conforming DIMM organizations are shown in Table A-2..
Table A-2. DIMM Organization
DIMM 0 (J38)
System
Memory
Module
DIMM 1 (J39)
System
Memory
Module
Total
System
Memory
DIMM 2 (J36)
Buffer/Cache
Memory
Module
DIMM 3 (J37)
Buffer/Cache
Memory
Module
Total
Buffer/Cache
Memory
Total
Memory
256MB 256MB 512MB 256MB 256MB 512MB 1GB
256MB 256MB 512MB 512MB 512MB 1GB 1.5GB
256MB 256MB 512MB 1GB 1GB 2GB 2.5GB
256MB 256MB 512MB 2GB 2GB 4GB 4.5GB