Specifications

Gigabit Multimedia Serial Link Deserializer
with LVDS System Interface
MAX9268
8 ______________________________________________________________________________________
Pin Description (continued)
PIN NAME FUNCTION
10 GPIO1
General-Purpose I/O 1. Open-drain general-purpose input/output with internal 60kI (typ)
pullup resistor to IOVDD. GPIO1 is high impedance during power-up and when PWDN = low.
11 DVDD
3.3V Digital Power Supply. Bypass DVDD to GND with 0.1FF and 0.001FF capacitors as close
as possible to the device with the smaller capacitor closest to DVDD.
12, 22, 38 GND Digital and I/O Ground
13 RX/SDA
Receive/Serial Data. UART receive or I
2
C serial-data input/output with internal 30kI (typ)
pullup to IOVDD. In UART mode, RX/SDA is the Rx input of the MAX9268’s UART. In I
2
C
mode, RX/SDA is the SDA input/output of the MAX9268’s I
2
C master.
14 TX/SCL
Transmit/Serial Clock. UART transmit or I
2
C serial-clock output with internal 30kI (typ) pullup
to IOVDD. In UART mode, TX/SCL is the Tx output of the MAX9268’s UART. In I
2
C mode, TX/
SCL is the SCL output of the MAX9268’s I
2
C master.
15 PWDN Power-Down. Active-low power-down input requires external pulldown or pullup resistor.
16 WS I
2
S Word-Select Output
17 SCK I
2
S Serial-Clock Output
18 SD/CNTL0 I
2
S Serial-Data/Control Output. Disable I
2
S to use SD/CNTL0 as an additional control output.
19 CNTL1
Control Output 1. CNTL1 is not active in 3-channel mode and remains low. To use CNTL1,
drive BWS high (4-channel mode) and set DISCNTL = 0. CNTL1 is mapped from DOUT27.
20 CNTL2/MCLK
Control 2/MCLK Output. CNTL2/MCLK is not active in 3-channel mode and remains low.
To use CNTL2/MCLK, drive BWS high (4-channel mode). CNTL2/MCLK is mapped from
DOUT28. CNTL/MCLK can also be used to output MCLK (see the Additional MCLK Output for
Audio Applications section).
21, 39 IOVDD
I/O Supply Voltage. 1.8V to 3.3V logic I/O power supply. Bypass IOVDD to GND with
0.1FF and 0.001FF capacitors as close as possible to the device with the smaller
capacitor closest to IOVDD.
25, 26, 29, 30,
33–36
TXOUT_+,
TXOUT_-
Differential LVDS Data Outputs. Set BWS = low (3-channel mode) to use TXOUT0_ to
TXOUT2_. Set BWS = high (4-channel mode) to use TXOUT0_ to TXOUT3_.
27, 28
TXCLKOUT+,
TXCLKOUT-
Differential LVDS Output for the LVDS Clock
40 ADD0
Address Selection Input 0. Three-level input to select the MAX9268’s device address
(see Table 2). The state of ADD0 latches upon power-up or when resuming from power-down
mode (PWDN = low).
41 ADD1
Address Selection Input 1. Three-level input to select the MAX9268’s device address
(see Table 2). The state of ADD1 latches upon power-up or when resuming from power-down
mode (PWDN = low).
42 LOCK
Open-Drain Lock Output with Internal 60kI (typ) Pullup to IOVDD. LOCK = high indicates
PLLs are locked with correct serial-word-boundary alignment. LOCK = low indicates PLLs are
not locked or incorrect serial-word-boundary alignment. LOCK remains low when the
configuration link is active. LOCK is high impedance when PWDN = low.
43 ERR
Active-Low, Open-Drain Video Data Error Output with Internal 60kI (typ) Pullup to IOVDD.
ERR goes low when the number of decoding errors during normal operation exceeds a pro-
grammed error threshold, or when at least one PRBS error is detected during PRBS test. ERR
is high impendence when PWDN = low.