Specifications

Gigabit Multimedia Serial Link Deserializer
with LVDS System Interface
MAX9268
_______________________________________________________________________________________ 7
Pin Description
Pin Configuration
GPIO0
4
AVDD
5
IN+
6
IN-
7
AGND
8
EQS
9
GPIO1
10
DVDD
11
GND
12
BWS
1
INT
2
CDS
3
33 32 31 30 29 28 27 26 25
EP
36 35 34
AGND
AVDD
GND
IOVDD
CNTL2/MCLK
CNTL1
SD/CNTL0
SCK
WS
PWDN
TX/SCL
RX/SDA
AGND
GND
IOVDD
ADD0
ADD1
LOCK
ERR
MS
SSEN
DRS
AVDD
AGND
37
38
39
40
41
42
43
44
45
46
47
48
TOP VIEW
24
23
22
21
20
19
18
17
16
15
14
13
MAX9268
TXOUT1+ AVDD AGND TXOUT2- TXOUT2+ TXCLKOUT- TXCLKOUT+ TXOUT3- TXOUT3+ TXOUT0- TXOUT0+ TXOUT1-
+
TQFP
PIN NAME FUNCTION
1
BWS
Bus-Width Select. Output width selection requires external pulldown or pullup resistor. Set
BWS = low for 3-channel mode. Set BWS = high for 4-channel mode.
2 INT
Interrupt Input. Requires external pulldown or pullup resistor. A transition on the MAX9268’s
INT input toggles the GMSL serializer’s INT output.
3 CDS
Control Direction Selection. Control link direction selection input requires external pulldown or
pullup resistor. Set CDS = low for FC on the GMSL serializer side of the serial link. Set CDS =
high for FC on the MAX9268 side of the serial link.
4 GPIO0
General-Purpose I/O 0. Open-drain, general-purpose input/output with internal 60kI (typ)
pullup resistor to IOVDD. GPIO0 is high impedance during power-up and when PWDN = low.
5, 23, 32, 47 AVDD
3.3V Analog Power Supply. Bypass AVDD to AGND with 0.1FF and 0.001FF capacitors as
close as possible to the device with the smaller capacitor closest to AVDD.
6, 7 IN+, IN- Differential CML Input. Differential input of the serial link.
8, 24, 31, 37, 48 AGND Analog Ground
9 EQS
Equalizer Select Input. EQS requires external pulldown or pullup resistor. The state of EQS
latches upon power-up or when resuming from power-down mode (PWDN = low). Set
EQS = low for 10.7dB equalizer boost (EQTUNE = 1001). Set EQS = high for 5.2dB
equalizer boost (EQTUNE = 0100).