Specifications

Gigabit Multimedia Serial Link Deserializer
with LVDS System Interface
MAX9268
_______________________________________________________________________________________ 3
DC ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= V
DVDD
= 3.0V to 3.6V, V
IOVDD
= 1.7V to 3.6V, R
L
= 100Ω Q1% (differential), T
A
= -40NC to +105NC, unless otherwise noted.
Typical values are at V
AVDD
= V
DVDD
= V
IOVDD
= 3.3V, T
A
= +25NC.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
I
2
C AND UART I/O, OPEN-DRAIN OUTPUTS (RX/SDA, TX/SCL, LOCK, ERR, GPIO_)
High-Level Input Voltage V
IH2
0.7 x
V
IOVDD
V
Low-Level Input Voltage V
IL2
0.3 x
V
IOVDD
V
Input Current I
IN2
V
IN
= 0V to
V
IOVDD
(Note 2)
RX/SDA, TX/SCL -110 +1
FA
LOCK, ERR, GPIO_
-80 +1
Low-Level Output Voltage V
OL2
I
OUT
= 3mA
V
IOVDD
= 1.7V to 1.9V 0.4
V
V
IOVDD
= 3.0V to 3.6V 0.3
DIFFERENTIAL OUTPUT FOR REVERSE CONTROL CHANNEL (IN+, IN-)
Differential High Output Peak
Voltage, (V
IN+
) - (V
IN-
)
V
ROH
No high-speed data transmission
(Figure 1)
30 60 mV
Differential Low Output Peak
Voltage, (V
IN+
) - (V
IN-
)
V
ROL
No high-speed data transmission
(Figure 1)
-60 -30 mV
DIFFERENTIAL INPUTS (IN+, IN-)
Differential High Input Threshold
(Peak) Voltage, (V
IN+
) - (V
IN-
)
V
IDH(P)
Figure 2 40 90 mV
Differential Low Input Threshold
(Peak) Voltage, (V
IN+
) - (V
IN-
)
V
IDL(P)
Figure 2 -90 -40 mV
Input Common-Mode Voltage
((V
IN+
) + (V
IN-
))/2
V
CMR
1 1.3 1.6 V
Differential Input Resistance
(Internal)
R
I
80 100 130
I
THREE-LEVEL LOGIC INPUTS (ADD0, ADD1)
High-Level Input Voltage V
IH
0.7 x
V
IOVDD
V
Low-Level Input Voltage V
IL
0.3 x
V
IOVDD
V
Mid-Level Input Current I
INM
ADD0 and ADD1 open or connected
to a driver with output in high impedance
(Note 3)
-10 +10
FA
Input Current I
IN
ADD0 and ADD1 = high or low,
PWDN = high or low
-150 +150
FA
Input Clamp Voltage V
CL
I
CL
= -18mA -1.5 V
LVDS OUTPUTS (TXOUT__, TXCLKOUT_)
Differential Output Voltage V
OD
Figure 3 250 450 mV
Change in V
OD
Between
Complementary Output States
DV
OD
Figure 3 25 mV
Output Offset Voltage V
OS
Figure 3 1.125 1.375 V
Change in V
OS
Between
Complementary Output States
DV
OS
Figure 3 25 mV