Specifications
Gigabit Multimedia Serial Link Deserializer
with LVDS System Interface
MAX9268
18 _____________________________________________________________________________________
Reserved Bit (RES)/CNTL1
In 4-channel mode, the MAX9268 deserializes serial-
data bit 27 to both RES and CNTL1 by default (both
DISCNTL and DISRES = 0). Setting DISRES (D2 of
register 0x14) = 1 forces RES low. Setting DISCNTL1 (D3
of register 0x14) = 1 forces CNTL1 low.
Reverse Control Channel
The GMSL serializer uses the reverse control
channel to receive I
2
C/UART and interrupt signals from
the MAX9268 in the opposite direction of the video
stream. The reverse control channel and forward video
data coexist on the same twisted pair forming a bidirec-
tional link. The reverse control channel operates inde-
pendently from the forward control channel. The reverse
control channel is available 500Fs after power-up. The
GMSL serializer temporarily disables the reverse control
channel for 350Fs after starting/stopping the forward
serial link.
Data-Rate Selection
The MAX9268 uses the DRS input to set the TXCLKOUT_
frequency. Set DRS high for a TXCLKOUT_ frequency
of 6.25MHz to 12.5MHz (4-channel mode), or 8.33MHz
to 16.66MHz (3-channel mode). Set DRS low for normal
operation with a TXCLKOUT_ frequency of 12.5MHz
to 78MHz (4-channel mode), or 16.66MHz to 104MHz
(3-channel mode).
Audio Channel
The I
2
S audio channel supports audio sampling rates
from 8kHz to 192kHz and audio word lengths from 4 bits
to 32 bits. The audio bit clock (SCK) does not have to
be synchronized with TXCLKOUT_. The GMSL serializer
automatically encodes audio data into a single bit stream
Figure 14. 3-Channel Mode Serial Link Data Format
Figure 15. 4-Channel Mode Serial Link Data Format
NOTE: TYPICAL LOCATIONS OF THE RGB DATA AND CONTROL SIGNALS.
DOUT0
LVDS
DATA
(3 CHANNELS)
DOUT1 DOUT17 DOUT18 DOUT19 DOUT20 ACB FCC PCB
24 BITS
AUDIO
CHANNEL BIT
FORWARD
CONTROL-
CHANNEL BIT
PACKET
PARITY
CHECK BIT
R0 R1 B5 HS VS DE
DOUT21
LVDS
DATA
(TXOUT3_)
DOUT22 DOUT25 DOUT26 DOUT27 DOUT28 ACB FCC PCB
32 BITS
AUDIO
CHANNEL/CNTL0
BIT
FORWARD
CONTROL-
CHANNEL BIT
PACKET
PARITY
CHECK BIT
R6 R7 B6
DOUT24
G7
DOUT23
G6 B7 CNTL2
RES/CNTL1*
DOUT1
LVDS
DATA
(TXOUT[2:0]_)
DOUT18 DOUT19 DOUT20
R1
DOUT0
R0 HS
DOUT17
B5 VS DE
*DOUT27 OUTPUTS TO LVDS DATA (TXOUT3_) AND/OR EXTERNAL PIN (CNTL1).
NOTE: TYPICAL LOCATIONS OF THE LVDS RGB DATA AND CONTROL SIGNALS.