Specifications

Gigabit Multimedia Serial Link Deserializer
with LVDS System Interface
MAX9268
______________________________________________________________________________________ 17
Figure 12. LVDS Output Timing
Figure 13. Typical Panel Clock and Bit Assignment
DOUT1
CYCLE N
TXOUT0+/TXOUT0-
TXCLKOUT+
TXCLKOUT-
TXOUT1+/TXOUT1-
TXOUT2+/TXOUT2-
DOUT0 DOUT6 DOUT5 DOUT4 DOUT3 DOUT2 DOUT1 DOUT0
DOUT8 DOUT7 DOUT13 DOUT12 DOUT11 DOUT10 DOUT9 DOUT8 DOUT7
DOUT15 DOUT14 DOUT20 DOUT19 DOUT18 DOUT17 DOUT16 DOUT15 DOUT14
TXOUT3+/TXOUT3-
CNTL1
DOUT22 DOUT21
DOUT27
CNTL2/MCLK
DOUT28
SD/CNTL0
*ONLY WHEN I
2
S IS DISABLED.
SD*
DOUT27 DOUT26 DOUT25 DOUT24 DOUT23 DOUT22 DOUT21
CYCLE N-1
R1
CYCLE N-1 CYCLE N
TXOUT0+/TXOUT0-
TXCLKOUT+
TXCLKOUT-
TXOUT1+/TXOUT1-
TXOUT2+/TXOUT2-
R0 G0 R5 R4 R3 R2 R1 R0
G2 G1 B1 B0 G5 G4 G3 G2 G1
B3 B2 DE VS HS B5 B4 B3 B2
TXOUT3+/TXOUT3-
R7 R6 RES B7 B6 G7 G6 R7 R6