Specifications

Gigabit Multimedia Serial Link Deserializer
with LVDS System Interface
MAX9268
16 _____________________________________________________________________________________
Typical Bitmapping and
Bus-Width Selection
The LVDS output has two selectable widths: 3-channel
and 4-channel. The MAX9268 outputs 3- or 4-channel
LVDS (Table 3). Serial data is mapped to outputs on the
MAX9268 according to Figures 12 and 13. In 3-chan-
nel mode, TXOUT3_ and CNTL1, CNTL2/MCLK are not
available. For both modes, the SD/CNTL0, SCK, and WS
pins are for I
2
S audio when audio is enabled. With audio
disabled, SD/CNTL0 becomes control signal CNTL0.
The MAX9268 outputs clock rates from 8.33MHz to
104MHz for 3-channel mode and 6.25MHz to 78MHz for
4-channel mode.
Serial Link Signaling and Data Format
The GMSL high-speed serial link uses CML signaling
with programmable preemphasis and AC-coupling. The
GMSL deserializer uses AC-coupling and programmable
channel equalization. When using both the preemphasis
and equalization, including internally generated over-
head bits, the GMSL link operates up to 3.125Gbps over
STP cable lengths of 15m or greater. The payload data
rate, which is the data rate available to the user or the
data rate after subtracting overhead, is 2.5Gbps.
The GMSL serializer scrambles and encodes the input
data and sends the 8b/10b coded signal through the
serial link. The MAX9268 deserializer recovers the
embedded serial clock and then samples, decodes, and
descrambles before outputting the data. Figures 14 and
15 show the serial-data packet format after unscrambling
and 8b/10b decoding. In 3-channel or 4-channel mode,
21 or 28 bits map to the TXOUT_ _ LVDS outputs. Serial-
data bits 27 and 28 map to control outputs in 4-channel
mode. The audio channel bit (ACB) contains an encoded
audio signal derived from the three I
2
S signals (SD/
CNTL0, SCK, and WS). The forward control-channel
(FCC) bit carries the forward control data. The last bit
(PCB) is the parity bit of the previous 23 or 31 bits.
*See the Reserved Bit (RES)/CNTL1 section for details.
Table 3. Bus-Width Selection Using BWS
OUTPUT BITS
3-CHANNEL MODE
(BWS = LOW)
4-CHANNEL MODE
(BWS = HIGH)
TYPICAL BITMAPPING
AUXILIARY SIGNALS
MAPPING
TYPICAL BITMAPPING
AUXILIARY SIGNALS
MAPPING
DOUT[0:5] R[0:5] — R[0:5] —
DOUT[6:11] G[0:5] — G[0:5] —
DOUT[12:17] B[0:5] — B[0:5] —
DOUT[18:20] HS, VS, DE — HS, VS, DE —
DOUT[21:22] Not used Not used R6, R7 —
DOUT[23:24] Not used Not used G6, G7 —
DOUT[25:26] Not used Not used B6, B7 —
DOUT27 Not used Not used RES* CNTL1*
DOUT28 Not used Not used — CNTL2/MCLK
SD — SD/CNTL0 — SD/CNTL0