Specifications

Gigabit Multimedia Serial Link Deserializer
with LVDS System Interface
MAX9268
12 _____________________________________________________________________________________
Figure 6. Single-Ended Output Rise-and-Fall Times Figure 7. LVDS Output Pulse Position Measurement
Figure 8. Deserializer Delay
Figure 10. Power-Up Delay
Figure 9. Lock Time
Figure 11. Output I
2
S Timing Parameters
0.8 x V
I0VDD
0.2 x V
I0VDD
t
F
t
R
C
L
SINGLE-ENDED OUTPUT LOAD
MAX9268
EXPANDED TIME SCALE
N
FIRST BIT
IN+/IN-
TXOUT_+/
TXOUT_-
TXCLKOUT+/-
N+1
N-1
N
FIRST BIT
t
SD
N+2...
IN+ - IN-
LOCK
t
LOCK
PWDN MUST BE HIGH
V
OH
(TXCLKOUT+) -
(TXCLKOUT-)
(TXOUT_+) -
(TXOUT_-)
t
PPOS0
t
PPOS1
t
PPOS2
t
PPOS3
t
PPOS4
t
PPOS5
t
PPOS6
IN+/-
LOCK
t
PU
PWDN
V
OH
V
IH1
WS
t
DVA
t
DVB
t
DVA
t
F
t
DVB
t
R
SCK
SD