Specifications

33Maxim Integrated
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
MAX9263/MAX9264
In the event of a missed acknowledge, the FC should
assume there was an error in the packet transmission or
response. In base mode, the FC must keep the UART Tx/
Rx lines high no more than four bit times between bytes
in a packet. Keep the UART Tx/Rx lines high for 16 bit-
times before starting to send a new packet.
As shown in Figure 28, the remote-side device converts
the packets going to or coming from the peripherals from
the UART format to the I
2
C format and vice versa. The
remote device removes the byte number count and adds
or receives the ACK between the data bytes of I
2
C. The
I
2
C’s data rate is the same as the UART data rate.
Interfacing Command-Byte-Only I
2
C Devices
The serializer and deserializer UART-to-I
2
C conver-
sion interfaces with devices that do not require register
addresses, such as the MAX7324 GPIO expander. In
this mode, the I
2
C master ignores the register address
byte and directly reads/writes the subsequent data bytes
(Figure 29). Change the communication method of the
I
2
C master using the I2CMETHOD bit. I2CMETHOD = 1
sets command-byte-only mode, while I2CMETHOD = 0
sets normal mode where the first byte in the data stream
is the register address.
Bypass Mode
In bypass mode, the serializer/deserializer ignore UART
commands from the FC and the FC communicates with
the peripherals directly using its own defined UART pro-
tocol. The FC cannot access the serializer/deserializer’s
registers in this mode. Peripherals accessed through the
forward control channel using the UART interface need
to handle at least one PCLKIN period ±10ns of jitter due
to the asynchronous sampling of the UART signal by
PCLKIN. Set MS = high to put the control channel into
bypass mode. For applications with the FC connected to
the deserializer, (CDS is high) there is a 1ms wait time
between setting MS high and the bypass control channel
being active. There is no delay time when switching to
bypass mode when the FC is connected to the serial-
izer (CDS = low). Do not send a logic-low value longer
than 100Fs to ensure proper interrupt functionality.
Bypass mode accepts bit rates down to 10kbps in either
direction. See the Interrupt Control section for interrupt
functionality limitations. The control-channel data pattern
should not be held low longer than 100Fs if interrupt
control is used.
Figure 28. Format Conversion Between GMSL UART and I
2
C with Register Address (I2CMETHOD = 0)
11
SYNC FRAME REGISTER ADDRESS NUMBER OF BYTESDEVICE ID + WR DATA 0
DEV ID A
11 11 11 11
DATA N
11 11
S
1 11
ACK FRAME
7
: MASTER TO SLAVE
8
SERIALIZER/DESERIALIZER PERIPHERAL
W
1
REG ADDR
8
A
1181
11
SYNC FRAME REGISTER ADDRESS NUMBER OF BYTESDEVICE ID + RD
11 11 11 11
ACK FRAME
DATA 0
11
DATA N
11
UART-TO-I
2
C CONVERSION OF WRITE PACKET (I2CMETHOD = 0)
UART-TO-I
2
C CONVERSION OF READ PACKET (I2CMETHOD = 0)
S: START P: STOP A: ACKNOWLEDGE
: SLAVE TO MASTER
DATA 0A DATA NAP
DEV ID AS
117
W
1
DEV ID AS
117
R
1
DATA NP
18
A
1
DATA 0
8
A
1
REG ADDR
8
A
1
FC
SERIALIZER/DESERIALIZER
FC
SERIALIZER/DESERIALIZER
SERIALIZER/DESERIALIZER PERIPHERAL