Specifications

31Maxim Integrated
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
MAX9263/MAX9264
the maximum audio sampling rate for various PCLKIN
frequencies. Spread-spectrum settings do not affect
the I
2
S data rate or WS clock frequency.
Additional MCLK Output for
Audio Applications
Some audio DACs, such as the MAX9850, do not require
a synchronous main clock (MCLK), while other DACs
require MCLK to be a specific multiple of WS. If an audio
DAC chip needs the MCLK to be a multiple of WS, use
an external PLL to regenerate the required MCLK from
PCLKOUT or SCK.
For audio applications that cannot directly use PCLKOUT,
the MAX9264 provides a divided MCLK output on
DOUT28/MCLK at the expense of one less control line
in 32-bit mode (24-bit mode is not affected). By default,
DOUT28/MCLK operates as a parallel data output, and
MCLK is turned off. Set MCLKDIV (MAX9264 register
0x12, D[6:0]) to a non-zero value to enable the MCLK
output. Set MCLKDIV to 0x00 to disable MCLK and set
DOUT28/MCLK as a parallel data output.
The output MCLK frequency is:
SRC
MCLK
f
f
MCLKDIV
=
where f
SRC
is the MCLK source frequency (Table 3)
MCLKDIV is the divider ratio from 1 to 127
Choose MCLKDIV values so that f
MCLK
is not greater
than 60MHz. MCLK frequencies derived from PCLKIN
(MCLKSRC = 0) are not affected by spread-spectrum
settings in the deserializer. Enabling spread spectrum
in the serializer, however, introduces spread spectrum
into MCLK. Spread-spectrum settings of either device
do not affect MCLK frequencies derived from the internal
oscillator. The internal oscillator frequency ranges from
100MHz to 150MHz over all process corners and operat-
ing conditions.
Control Channel and Register Programming
The control channel is available for the FC to send and
receive control data over the serial link simultaneously
with the high-speed data. Configuring the CDS pin allows
the FC to control the link from either the serializer or the
deserializer side to support video-display or image-
sensing applications. The control channel between the
FC and serializer or deserializer runs in base mode or
bypass mode according to the mode selection (MS)
input of the device connected to the FC. Base mode is
a half-duplex control channel and the bypass mode is a
full-duplex control channel.
Base Mode
In base mode, the FC is the host and can access the
core and HDCP registers of both the serializer and
deserializer from either side of the link by using the
GMSL UART protocol. The FC can also program the
peripherals on the remote side by sending the UART
packets to the serializer or deserializer, with the UART
packets converted to I
2
C by the device on the remote
side of the link (deserializer for LCD or serializer for
image-sensing applications). The FC communicates
with a UART peripheral in base mode (through INTTYPE
register settings), using the half-duplex default GMSL
UART protocol of the serializer/deserializer. The device
addresses of the serializer and deserializer in base
mode are programmable. The default value is 0x80 for
the serializer and 0x90 for the deserializer.
When the peripheral interface uses I
2
C (default), the
serializer/deserializer convert packets to I
2
C that have
device addresses different from those of the serializer or
deserializer. The converted I
2
C bit rate is the same as
the original UART bit rate.
The deserializer uses a proprietary differential line cod-
ing to send signals back towards the serializer. The
speed of the control channel ranges from 9.6kbps to
Table 3. Deserializer f
SRC
Settings
MCLKSRC SETTING
(REGISTER 0x12, D7)
DATA RATE SETTING BIT WIDTH SETTING
MCLK SOURCE
FREQUENCY (fSRC)
0
High speed
24-bit mode 3 x fPCLKIN
32-bit mode 4 x fPCLKIN
Low speed
24-bit mode 6 x fPCLKIN
32-bit mode 8 x fPCLKIN
1
— —
Internal oscillator
(120MHz typ)