Specifications
30 Maxim Integrated
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
MAX9263/MAX9264
bit carries the forward control data. The last bit (PCB) is
the parity bit of the previous 23 or 31 bits.
Reverse Control Channel
The serializer uses the reverse control channel to receive
I
2
C/UART and interrupt signals from the deserializer in
the opposite direction of the video stream. The reverse
control channel and forward video data coexist on
the same twisted pair forming a bidirectional link. The
reverse control channel operates independently from the
forward control channel. The reverse control channel is
available 500Fs after power-up. The serializer temporar-
ily disables the reverse control channel for 350Fs after
starting/stopping the forward serial link.
Data-Rate Selection
The serializer/deserializer use the DRS input to set the
PCLKIN frequency range. Set DRS high for a PCLKIN
frequency range of 6.25MHz to 12.5MHz (32-bit mode)
or 8.33MHz to 16.66MHz (24-bit mode). Set DRS low
for normal operation with a PCLKIN frequency range
of 12.5MHz to 78MHz (32-bit mode) or 16.66MHz to
104MHz (24-bit mode).
Audio Channel
The I
2
S audio channel supports audio sampling rates
from 8kHz to 192kHz and audio word lengths from 4 bits
to 32 bits. The audio bit clock (SCK) does not have to be
synchronized with PCLKIN. The serializer automatically
encodes audio data into a single bit stream synchronous
with PCLKIN. The deserializer decodes the audio stream
and stores audio words in a FIFO. Audio rate detection
uses an internal oscillator to continuously determine the
audio data rate and output the audio in I
2
S format. The
audio channel is enabled by default. When the audio
channel is disabled, the audio data on the serializer and
deserializer are treated as an additional parallel signal
(DIN_/DOUT_).
Since the audio data sent through the serial link is
synchronized with PCLKIN, low PCLKIN frequencies
limit the maximum audio sampling rate. Table 2 lists
Table 2. Maximum Audio WS Frequency (kHz) for Various PCLKIN Frequencies
Figure 23. 32-Bit Mode Serial Link Data Format
DIN0
R0
RGB DATA CONTROL BITS RGB DATA ADDITIONAL
VIDEO DATA/
CONTROL BITS
AUDIO
CHANNEL
BIT
FORWARD
CONTROL-
CHANNEL BIT
PACKET
PARITY
CHECK BIT
R1
DIN1 DIN17
B5 HS VS DE R6 R7
32 BITS
G6 G7 B6 B7
DIN18 DIN19 DIN20 DIN21 DIN22 DIN23 DIN24 DIN25 DIN26 DIN27 DIN28 ACB FCC PCB
NOTE: LOCATIONS OF THE RGB DATA ARE INTERCHANGABLE
ACCORDINGLY ON BOTH SIDES OF THE LINK.
ONLY DIN[17:0], DIN[26:21] AND ACB HAVE HDCP ENCRYPTION.
WORD
LENGTH
(bits)
PCLKIN FREQUENCY
(DRS = LOW) (MHz)
PCLKIN FREQUENCY
(DRS = HIGH) (MHz)
12.5 15 16.6 > 20 6.25 7.5 8.33 > 10
8
> 192 > 192 > 192 > 192 > 192 > 192 > 192 > 192
16
> 192 > 192 > 192 > 192 > 192 > 192 > 192 > 192
18
185.5 > 192 > 192 > 192 185.5 > 192 > 192 > 192
20
174.6 > 192 > 192 > 192 174.6 > 192 > 192 > 192
24
152.2 182.7 > 192 > 192 152.2 182.7 > 192 > 192
32
123.7 148.4 164.3 > 192 123.7 148.4 164.3 > 192