Specifications
26 Maxim Integrated
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
MAX9263/MAX9264
Figure 16. Deserializer Clock Output High and Low Times
Figure 17. Deserializer Output Rise and Fall Times
Figure 14. Test Circuit for Differential Input Measurement Figure 15. Deserializer Worst-Case Pattern Output
V
IN+
R
L
/2
R
L
/2
C
IN
C
IN
V
ID(P)
IN+
IN-
V
ID(P) =
| V
IN+
- V
IN-
|
V
CMR =
(V
IN+
+ V
IN-
)/2
V
IN-
_
+
_
_
+
PCLKOUT
DOUT_
NOTE: PCLKOUT PROGRAMMED FOR RISING LATCH EDGE.
V
OL MAX
t
HIGH
t
LOW
t
T
V
OH MIN
PCLKOUT
0.8 x V
I0VDD
0.2 x V
I0VDD
t
F
t
R
C
L
SINGLE-ENDED OUTPUT LOAD
MAX9264