Specifications

16 Maxim Integrated
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
MAX9263/MAX9264
MAX9264 Pin Description
PIN NAME FUNCTION
1
ENABLE
Active-Low Parallel Output-Enable Input. Requires an external pulldown or pullup resistor. Set
ENABLE = low to enable PCLKOUT, SD, SCK, WS, and DOUT_. Set ENABLE = high to put
PCLKOUT, SD, SCK, WS, and DOUT_ into high impedance.
2 BWS
Bus-Width Select. BWS requires an external pulldown or pullup resistor. Set BWS = low for
24-bit mode. Set BWS = high for 32-bit mode.
3 INT
Interrupt Input. INT requires an external pullup or pulldown resistor. A transition on the
deserializer’s INT input toggles the serializer’s INT output.
4 CDS
Control Direction Selection. Control link direction selection input requires external pulldown or
pullup resistor. Set CDS = high for UART connection of a FC as control-channel master. Set
CDS = low for peripheral connection as a control-channel I
2
C or UART slave.
5 GPIO0
GPIO0. Open-drain general-purpose input/output with an internal 60kI pullup resistor to
IOVDD. GPIO0 is high impedance during power-up and when PWDN = low.
6 ES
Edge Select. PCLKOUT edge-selection input requires an external pulldown or pullup resistor.
Set ES = low for a rising-edge trigger. Set ES = high for a falling-edge trigger.
7, 63 AVDD
3.3V Analog Power Supply. Bypass AVDD to AGND with 0.1FF and 0.001FF capacitors as
close as possible to the device with the smaller capacitor closest to AVDD.
8, 9 IN+, IN-
Differential CML Input Q. Differential inputs of the serial link.
10, 64 AGND Analog Ground
11 EQS
Equalizer Select Input Requires an External Pulldown or Pullup Resistor. The state of EQS
latches upon power-up or when resuming from power-down mode (PWDN = low). Set EQS =
low for 10.7dB equalizer boost (EQTUNE = 1001). Set EQS = high for 5.2dB equalizer boost
(EQTUNE = 0100).
12 GPIO1
GPIO1. Open-drain general-purpose input/output with an internal 60kI pullup resistor to
IOVDD. GPIO1 is high impedance during power-up and when PWDN = low.
13 DCS
Drive Current Select. Driver current-selection input requires an external pulldown or
pullup resistor to IOVDD. Set DCS = high for stronger parallel data and clock output drivers.
Set DCS = low for normal parallel data and clock drivers. See the MAX9264 DC Electrical
Characteristics table.
14 MS
Mode Select. Control-channel mode selection input requires an external pulldown or
pullup resistor. MS sets the control-link mode when CDS = high. See the Control-Channel and
Register Programming section. MS sets autostart mode when CDS = low. See Table 11.
15 DVDD
3.3V Digital Power Supply. Bypass DVDD to DGND with 0.1FF and 0.001FF capacitors as
close as possible to the device with the smaller capacitor closest to DVDD.
16 DGND Digital Ground
17 RX/SDA
Receive/Serial Data. UART receive or I
2
C serial-data input/output with internal 30kI pullup to
IOVDD. In UART mode, RX/SDA is the Rx input of the deserializer’s UART. In I
2
C mode,
RX/SDA is the SDA input/output of the deserializer’s I
2
C master. RX/SDA has an open-drain
driver and requires a pullup resistor.
18 TX/SCL
Transmit/Serial Clock. UART transmit or I
2
C serial-clock output with internal 30kI pullup to
IOVDD. In UART mode, TX/SCL is the Tx output of the deserializer’s UART. In I
2
C mode,
TX/SCL is the SCL output of the deserializer’s I
2
C master. TX/SCL is an open-drain driver and
requires a pullup resistor.