Specifications

15Maxim Integrated
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
MAX9263/MAX9264
MAX9263 Pin Description (continued)
PIN NAME FUNCTION
34
PWDN Active-Low, Power-Down Input. PWDN requires external pulldown or pullup resistor.
35 RX/SDA
Receive/Serial Data. UART receive or I
2
C serial-data input/output with internal 30kI pullup to
IOVDD. In UART mode, RX/SDA is the Rx input of the serializer’s UART. In I
2
C mode,
RX/SDA is the SDA input/output of the serializer’s I
2
C master. RX/SDA has an open-drain
driver and requires a pullup resistor.
36 TX/SCL
Transmit/Serial Clock. UART transmit or I
2
C serial-clock output with internal 30kI pullup to
IOVDD. In UART mode, TX/SCL is the Tx output of the serializer’s UART. In I
2
C mode,
TX/SCL is the SCL output of the serializer’s I
2
C master. TX/SCL is an open-drain driver and
requires a pullup resistor.
37 SSEN
Spread-Spectrum Enable. Serial link spread-spectrum enable input requires external
pulldown or pullup resistor. The state of SSEN latches upon power-up or when resuming from
power-down mode (PWDN = low). Set SSEN = high for Q0.5% spread spectrum on the serial
link. Set SSEN = low to use the serial link without spread spectrum.
38 LMN1 Line-Fault Monitor Input 1. See Figure 3 for details.
40, 41 OUT-, OUT+
Differential CML Output Q. Differential outputs of the serial link.
43 LMN0 Line-Fault Monitor Input 0. See Figure 3 for details.
44
LFLT
Line Fault, Active-Low Open-Drain Line-Fault Output. LFLT has a 60kI internal pullup
resistor. LFLT = low indicates a line fault. LFLT is output high when PWDN = low.
45 INT
Interrupt Output. Indicates remote-side interrupt requests. INT = low upon power-up and when
PWDN = low. A transition on the INT input of the deserializer toggles the serializer’s INT output.
46 DRS
Data-Rate Select. Data-rate range-selection input requires external pulldown or pullup
resistor. The state of DRS latches upon power-up or when resuming from power-down mode
(PWDN = low). Set DRS = high for PCLKIN frequencies of 8.33MHz to 16.66MHz
(24-bit mode) or 6.25MHz to 12.5MHz (32-bit mode). Set DRS = low for PCLKIN frequencies
of 16.66MHz to 104MHz (24-bit mode) or 12.5MHz to 78MHz (32-bit mode).
47 ES
Edge Select. PCLKIN trigger edge selection requires external pulldown or pullup resistor. Set
ES = low to trigger on the rising edge of PCLKIN. Set ES = high to trigger on the falling edge
of PCLKIN.
48 BWS
Bus-Width Select. BWS requires external pulldown or pullup resistor. Set BWS = low for 24-bit
mode. Set BWS = high for 32-bit mode.
49 DIN0
Data Input 0. Parallel data input with internal pulldown to GND. Encrypted when HDCP is
enabled (Table 1).
52–60 DIN[1:9]
Data Input [1:9]. Parallel data inputs with internal pulldown to GND. Encrypted when HDCP is
enabled (Table 1).
63, 64 DIN[10:11]
Data Input [10:11]. Parallel data inputs with internal pulldown to GND. Encrypted when HDCP
is enabled (Table 1).
— EP
Exposed Pad. EP is internally connected to AGND. MUST externally connect EP to the AGND
plane for proper thermal and electrical performance.