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HDCP Gigabit Multimedia Serial

Link Serializer/Deserializer

MAX9263/MAX9264

EVALUATION KIT AVAILABLE

19-5644; Rev 2; 9/14

General Description

The MAX9263/MAX9264 chipset extends Maxim’s gigabit

multimedia serial link (GMSL) technology to include high-

bandwidth digital content protection (HDCP) encryption

of video and audio data. The MAX9263 serializer, or

any HDCP-GMSL serializer, pairs with the MAX9264

deserializer, or any HDCP-GMSL deserializer, for the

transmission of control data and HDCP encrypted video

and audio data.

The parallel interface operates with a pixel clock up to

104MHz. Three inputs are for I

S audio, supporting a

sampling frequency to 192kHz and a sample depth to

32 bits. The embedded control channel forms a full-

duplex differential 9.6kbps to 1Mbps UART link between

the serializer and deserializer. A microcontroller (FC),

can be located on the serializer side of the link, on the

deserializer side of the link, or on both sides. The control

channel enables FC control of peripherals on the remote

side, such as backlight control, touch screen, and per-

form HDCP-related operations.

For driving longer cables, the serializer has program-

mable pre/deemphasis, and the deserializer has a pro-

grammable channel equalizer. The GMSL devices have

programmable spread spectrum on the serial (serializer)

and parallel (deserializer) output. The serial link input

and output meet ISO 10605 and IEC 61000-4-2 ESD

standards. The serializer core supply is 1.8V and the

deserializer core supply is 3.3V. The I/O supply is 1.8V to

3.3V. Both devices are available in a 64-pin TQFP pack-

age with an exposed pad and are specified over the

-40NC to +105NC automotive temperature range.

Applications

High-Resolution Automotive Navigation

Rear-Seat Infotainment

Megapixel Camera Systems

Benefits and Features

S Ideal for HDCP Video Applications

Supports Up to XGA (1280 x 768) or Dual-View

WVGA (2x 854 x 480)

Pre/Deemphasis and Equalization Allows 15m

Cable at Full Speed

Up to 192kHz, 32-Bit/Sample I

S Multiple Data Rates for System Flexibility

Up to 3.12Gbps Serial-Bit Rate

6.25MHz to 104MHz Pixel Clock

100kbps to 1Mbps UART and UART-to-I

Control Channel

S Reduces EMI and Shielding Requirements

Serial Output Programmable for 100mV to

400mV

Programmable Spread Spectrum Reduces EMI

Bypassable Input PLL for Jitter Attenuation

S Peripheral Features for System Power-Up and

Verification

Built-In PRBS Tester for BER Testing of the

Serial Link

Interrupt Transmission from Deserializer to

Serializer

S Meets Rigorous Automotive and Industrial

Requirements

-40°C to +105°C Operating Temperature

ISO 10605 and IEC 61000-4-2 ESD Tolerance

Ordering Information

/V denotes an automotive qualified product.

+Denotes a lead(Pb)-free/RoHS-compliant package.

*EP = Exposed pad.

T = Tape and reel.

Blu-ray is a trademark of Blu-ray Disc Association.

PART TEMP RANGE PIN-PACKAGE

MAX9263GCB/V+

-40NC to +105NC

64 TQFP-EP*

MAX9263GCB/V+T

-40NC to +105NC

64 TQFP-EP*

MAX9264GCB/V+

-40NC to +105NC

64 TQFP-EP*

MAX9264GCB/V+T

-40NC to +105NC

64 TQFP-EP*

Summary of content (67 pages)

PAGE 1
EVALUATION KIT AVAILABLE MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer General Description The MAX9263/MAX9264 chipset extends Maxim’s gigabit multimedia serial link (GMSL) technology to include highbandwidth digital content protection (HDCP) encryption of video and audio data. The MAX9263 serializer, or any HDCP-GMSL serializer, pairs with the MAX9264 deserializer, or any HDCP-GMSL deserializer, for the transmission of control data and HDCP encrypted video and audio data.
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MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer ABSOLUTE MAXIMUM RATINGS AVDD to AGND MAX9263.............................................................-0.5V MAX9264.............................................................-0.5V DVDD to GND (MAX9263)....................................-0.5V DVDD to DGND (MAX9264)..................................-0.5V IOVDD to GND (MAX9263)...................................-0.5V IOVDD to IOGND (MAX9264)...............................-0.
PAGE 3
MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer MAX9263 DC ELECTRICAL CHARACTERISTICS (continued) (VAVDD = VDVDD = 1.7V to 1.9V, VIOVDD = 1.7V to 3.6V, RL = 100I Q1% (differential), TA = -40NC to +105NC, unless otherwise noted. Typical values are at VAVDD = VDVDD = VIOVDD = 1.8V, TA = +25NC.) PARAMETER Input Current Low-Level Output Voltage SYMBOL IIN2 VOL2 CONDITIONS MIN TYP MAX UNITS +5 FA VIN = 0 to VIOVDD (Note 2) VIOVDD = 1.7V to 1.9V IOUT = 3mA VIOVDD = 3.0V to 3.
PAGE 4
MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer MAX9263 DC ELECTRICAL CHARACTERISTICS (continued) (VAVDD = VDVDD = 1.7V to 1.9V, VIOVDD = 1.7V to 3.6V, RL = 100I Q1% (differential), TA = -40NC to +105NC, unless otherwise noted. Typical values are at VAVDD = VDVDD = VIOVDD = 1.8V, TA = +25NC.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ESD PROTECTION Human Body Model, RD = 1.
PAGE 5
MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer MAX9263 AC ELECTRICAL CHARACTERISTICS (VDVDD = VAVDD = 1.7V to 1.9V, VIOVDD = 1.7V to 3.6V, RL = 100I Q1% (differential), TA = -40NC to +105NC, unless otherwise noted. Typical values are at VDVDD = VAVDD = VIOVDD = 1.8V, TA = +25NC.) PARAMETER SYMBOL Deterministic Serial Output Jitter tDSOJ2 CONDITIONS MIN 3.
PAGE 6
MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer MAX9264 DC ELECTRICAL CHARACTERISTICS (continued) (VAVDD = VDVDD = 3.0V to 3.6V, VIOVDD = 1.7V to 3.6V, RL = 100I Q1% (differential), TA = -40NC to +105NC, unless otherwise noted. Typical values are at VAVDD = VDVDD = VIOVDD = 3.3V, TA = +25NC.
PAGE 7
MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer MAX9264 DC ELECTRICAL CHARACTERISTICS (continued) (VAVDD = VDVDD = 3.0V to 3.6V, VIOVDD = 1.7V to 3.6V, RL = 100I Q1% (differential), TA = -40NC to +105NC, unless otherwise noted. Typical values are at VAVDD = VDVDD = VIOVDD = 3.3V, TA = +25NC.) PARAMETER POWER SUPPLY SYMBOL CONDITIONS BWS = IOGND, fPCLKOUT = 16.6MHz BWS = IOGND, fPCLKOUT = 33.3MHz Worst-Case Supply Current (Figure 15, Note 3) IWCS BWS = IOGND, fPCLKOUT = 66.
PAGE 8
MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer MAX9264 AC ELECTRICAL CHARACTERISTICS (VAVDD = VDVDD = 3.0V to 3.6V, VIOVDD = 1.7V to 3.6V, RL = 100I Q1% (differential), TA = -40NC to +105NC, unless otherwise noted. Typical values are at VAVDD = VDVDD = VIOVDD = 3.3V, TA = +25NC.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS PARALLEL CLOCK OUTPUT (PCLKOUT) Clock Frequency Clock Duty Cycle Clock Jitter fPCLKOUT DC tJ BWS = IOGND, VDRS = VIOVDD 8.
PAGE 9
MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer MAX9264 AC ELECTRICAL CHARACTERISTICS (continued) (VAVDD = VDVDD = 3.0V to 3.6V, VIOVDD = 1.7V to 3.6V, RL = 100I Q1% (differential), TA = -40NC to +105NC, unless otherwise noted. Typical values are at VAVDD = VDVDD = VIOVDD = 3.3V, TA = +25NC.) PARAMETER Lock Time Power-Up Time SYMBOL tLOCK tPU CONDITIONS Figure 19 MIN TYP MAX Spread spectrum enabled 1.5 Spread spectrum disabled 1 UNITS ms Figure 20 2.
PAGE 10
MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer Typical Operating Characteristics (VAVDD = VDVDD = VIOVDD = 1.8V (MAX9263), VAVDD = VDVDD = VIOVDD = 3.3V (MAX9264), TA = +25NC, unless otherwise noted.) MAX9263 toc01 160 PRBS ON, HDCP ON SUPPLY CURRENT (mA) PREEMPHASIS = 0x0B TO 0x0F 130 120 PREEMPHASIS = 0x00 100 5 25 45 65 120 PREEMPHASIS = 0x01 TO 0x04 PREEMPHASIS = 0x00 5 20 35 50 65 80 PCLK FREQUENCY (MHz) PCLK FREQUENCY (MHz) MAX9264 SUPPLY CURRENT vs.
PAGE 11
MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer Typical Operating Characteristics (continued) (VAVDD = VDVDD = VIOVDD = 1.8V (MAX9263), VAVDD = VDVDD = VIOVDD = 3.3V (MAX9264), TA = +25NC, unless otherwise noted.) 0.5% SPREAD 0% SPREAD -20 -30 -40 -50 -60 -70 -80 2% SPREAD -90 30 31 32 33 34 35 -30 -40 -50 -60 -70 2% SPREAD -90 36 30 31 32 4% SPREAD 33 34 35 36 PCLK FREQUENCY (MHz) OUTPUT POWER SPECTRUM vs.
PAGE 12
MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer Pin Configurations CDS PWDN RX/SDA SSEN TX/SCL LMN1 AGND OUT- OUT+ AVDD LMN0 LFLT INT DRS BWS ES TOP VIEW 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 DIN0 49 32 MS GND 50 31 GND IOVDD 51 30 IOVDD DIN1 52 29 AUTOS DIN2 53 28 WS DIN3 54 27 SCK DIN4 55 26 SD DIN5 56 25 DIN28 MAX9263 DIN6 57 24 DIN27 DIN7 58 23 DIN26 DIN8 59 22 DIN25 DIN9 60 21 DIN24 GND 61 20 GND DVDD 62 19 DVDD EP*
PAGE 13
MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer DOUT23 DOUT22 DOUT21 DOUT20 DOUT19/VS DOUT18/HS DOUT17 DOUT16 DOUT15 DOUT14 DOUT13 DOUT12 DOUT11 DOUT10 DOUT9 TOP VIEW PCLKOUT Pin Configurations (continued) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 DOUT8 49 32 DOUT24 IOGND 50 31 IOGND IOVDD 51 30 IOVDD DOUT7 52 29 DOUT25 DOUT6 53 28 DOUT26 DOUT5 54 27 DOUT27 DOUT4 55 26 DOUT28/MCLK DOUT3 56 25 SD MAX9264 DOUT2 57 24 SCK DOUT1 58 23 WS
PAGE 14
MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer MAX9263 Pin Description PIN NAME FUNCTION 1–5 DIN[12:16] Data Input [12:16]. Parallel data inputs with internal pulldown to GND. Encrypted when HDCP is enabled (see Table 1). 6 PCLKIN Parallel Clock Input. Latches parallel data inputs and provides the PLL reference clock. 7, 30, 51 IOVDD I/O Supply Voltage. 1.8V to 3.3V logic I/O power supply. Bypass IOVDD to GND with 0.1FF and 0.
PAGE 15
MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer MAX9263 Pin Description (continued) PIN NAME 34 PWDN 35 36 37 FUNCTION Active-Low, Power-Down Input. PWDN requires external pulldown or pullup resistor. RX/SDA Receive/Serial Data. UART receive or I2C serial-data input/output with internal 30kI pullup to IOVDD. In UART mode, RX/SDA is the Rx input of the serializer’s UART. In I2C mode, RX/SDA is the SDA input/output of the serializer’s I2C master.
PAGE 16
MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer MAX9264 Pin Description PIN NAME FUNCTION 1 ENABLE Active-Low Parallel Output-Enable Input. Requires an external pulldown or pullup resistor. Set ENABLE = low to enable PCLKOUT, SD, SCK, WS, and DOUT_. Set ENABLE = high to put PCLKOUT, SD, SCK, WS, and DOUT_ into high impedance. 2 BWS 3 INT Interrupt Input. INT requires an external pullup or pulldown resistor.
PAGE 17
MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer MAX9264 Pin Description (continued) PIN NAME 19 PWDN FUNCTION Active-Low, Power-Down Input. PWDN requires an external pulldown or pullup resistor. Active-Low Open-Drain Video Data Error Output with Internal 60kI Pullup to IOVDD. ERR goes low when the number of decoding errors during normal operation exceed a programmed error threshold or when at least one PRBS error is detected during PRBS test.
PAGE 18
MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer MAX9264 Pin Description (continued) PIN NAME FUNCTION 52–59 DOUT[7:0] Data Output [7:0]. Parallel data outputs. Output data can be strobed on the selected edge of PCLKOUT. Encrypted when HDCP is enabled. See Table 1. SSEN Spread-Spectrum Enable Input. Serial link spread-spectrum enable input requires an external pulldown or pullup resistor.
PAGE 19
MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer Functional Diagrams (continued) PCLKOUT DOUT[17:0] SSPLL RGB[17:0] DOUT18/HS HS DOUT19/VS VS DOUT20 DE DOUT[26:21] (4-CH) RGB[23:18] (4-CH) DOUT27 (4-CH) CDRPLL CLKDIV RGB HDCP DECRYPT IN+ SERIAL TO PARALLEL HS VIDEO VS IN- DE HDCP KEYS FIFO HDCP CONTROL DIN[28:27] (4-CH) Tx DOUT28/MCLK (4-CH) AUDIO CML Rx AND EQ 8b/10b DECODE/ UNSCRAMBLE ACB HDCP DECRYPT REVERSE CONTROL CHANNEL FCC MAX9264 UART/I2C
PAGE 20
MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer RL/2 OUT+ VOD VOS OUT- RL/2 GND ((OUT+) + (OUT-))/2 OUTVOS(+) VOS(-) VOS(-) OUT+ DVOS = |VOS(+) - VOS(-)| VOD(+) VOD = 0V VOD(-) VOD(-) DVOD = |VOD(+) - VOD(-)| (OUT+) - (OUT-) Figure 1. Serializer Serial-Output Parameters OUT+ VOD(P) VOS VOD(D) OUT- SERIAL-BIT TIME Figure 2.
PAGE 21
MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer 1.7V TO 1.9V MAX9263 45.3kI* 45.3kI* LMN0 LMN1 4.99kI* OUTPUT LOGIC (OUT+) 4.99kI* TWISTED PAIR OUT+ OUT- 49.9kI* 49.9kI* CONNECTORS LFLT REFERENCE VOLTAGE GENERATOR OUTPUT LOGIC (OUT-) *Q1% TOLERANCE Figure 3. Line-Fault Detector Circuit PCLKIN DIN_ NOTE: PCLKIN PROGRAMMED FOR RISING LATCH EDGE. Figure 4.
PAGE 22
MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer tT VIH MIN tHIGH PCLKIN VIL MAX tR tF tLOW Figure 5. Serializer Parallel Input Clock Requirements START CONDITION (S) PROTOCOL BIT 7 MSB (A7) tLOW tSU;STA BIT 6 (A6) tHIGH BIT 0 (R/W) ACKNOWLEDGE (A) STOP CONDITION (P) 1/fSCL VIOVDD x 0.7 SCL VIOVDD x 0.3 tBUF tSP tf tr VIOVDD x 0.7 SDA VIOVDD x 0.3 tHD;STA tSU;DAT tHD;DAT tVD;DAT tVD;ACK tSU;STO Figure 6.
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MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer VIH MIN PCLKIN VIL MAX tSET tHOLD VIH MIN VIH MIN VIL MAX VIL MAX DIN_ NOTE: PCLKIN PROGRAMMED FOR RISING LATCHING EDGE. Figure 8. Serializer Input Setup and Hold Times EXPANDED TIME SCALE DIN_ N N+1 N+3 N+2 N+4 PCLKIN N-1 N OUT+/tSD FIRST BIT LAST BIT Figure 9.
PAGE 24
MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer PCLKIN tLOCK 350Fs SERIAL LINK INACTIVE SERIAL LINK ACTIVE REVERSE CONTROL CHANNEL AVAILABLE CHANNEL DISABLED REVERSE CONTROL CHANNEL ENABLED PWDN MUST BE HIGH Figure 10.
PAGE 25
MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer WS tHOLD tSCK tSET tLC SCK tHOLD tSET tHC SD Figure 12. Input I2S Timing Parameters RL/2 IN+ MAX9264 VOD REVERSE CONTROL-CHANNEL TRANSMITTER IN- VCMR RL/2 IN+ IN- IN- IN+ VCMR VROH 0.9 x VROH (IN+) - (IN-) 0.1 x VROH 0.1 x VROL tR 0.9 x VROL VROL tF Figure 13.
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MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer RL/2 IN+ VIN+ PCLKOUT VID(P) RL/2 IN- _ + _ VIN- + _ CIN CIN DOUT_ NOTE: PCLKOUT PROGRAMMED FOR RISING LATCH EDGE. VID(P) = | VIN+ - VIN- | VCMR = (VIN+ + VIN-)/2 Figure 14. Test Circuit for Differential Input Measurement Figure 15. Deserializer Worst-Case Pattern Output tT VOH MIN tHIGH PCLKOUT VOL MAX tLOW Figure 16. Deserializer Clock Output High and Low Times CL MAX9264 SINGLE-ENDED OUTPUT LOAD 0.
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MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer SERIAL-WORD LENGTH SERIAL WORD N SERIAL WORD N+1 SERIAL WORD N+2 IN+/LAST BIT FIRST BIT DOUT_ PARALLEL WORD N-1 PARALLEL WORD N-2 PARALLEL WORD N PCLKOUT tSD NOTE: PCLKOUT PROGRAMMED FOR RISING LATCHING EDGE. Figure 18. Deserializer Delay IN+/- IN+ - IN- PWDN tLOCK LOCK VIH1 tPU VOH LOCK VOH PWDN MUST BE HIGH Figure 19. Deserializer Lock Time Maxim Integrated Figure 20.
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MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer WS tDVA tR tDVB SCK tDVB tDVA tF SD Figure 21. Deserializer Output I2S Timing Parameters Detailed Description The MAX9263/MAX9264 serializer/deserializer chipset utilizes Maxim’s GMSL technology and HDCP. When HDCP is enabled, the serializer/deserializer encrypt video and audio data on the serial link. The serializer/ deserializer are backward compatible with the MAX9259/ MAX9260 serializer/deserializer.
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MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer HDCP Bitmapping and Bus-Width Selection Serial Link Signaling and Data Format The parallel input/outputs have two selectable modes, 24-bit mode and 32-bit mode. In 24-bit mode, DIN[28:21] are not available. For both modes, the SD, SCK, and WS pins are for I2S audio. The serializer/deserializer use pixel clock rates from 8.33MHz to 104MHz for 24-bit mode and 6.25MHz to 78MHz for 32-bit mode.
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MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer 32 BITS DIN0 DIN1 R0 R1 DIN17 DIN18 DIN19 DIN20 DIN21 DIN22 DIN23 DIN24 DIN25 DIN26 DIN27 DIN28 B5 HS RGB DATA VS DE R6 R7 G6 CONTROL BITS G7 B6 ACB FCC PCB B7 ADDITIONAL AUDIO VIDEO DATA/ CHANNEL BIT CONTROL BITS FORWARD CONTROLCHANNEL BIT RGB DATA NOTE: LOCATIONS OF THE RGB DATA ARE INTERCHANGABLE ACCORDINGLY ON BOTH SIDES OF THE LINK. ONLY DIN[17:0], DIN[26:21] AND ACB HAVE HDCP ENCRYPTION.
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MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer the maximum audio sampling rate for various PCLKIN frequencies. Spread-spectrum settings do not affect the I2S data rate or WS clock frequency. Additional MCLK Output for Audio Applications Some audio DACs, such as the MAX9850, do not require a synchronous main clock (MCLK), while other DACs require MCLK to be a specific multiple of WS.
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MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer 1Mbps in both directions. The serializer and deserializer automatically detect the control-channel bit rate in base mode. Packet bit rates can vary up to 3.5x from the previous bit rate. See the Changing the Clock Frequency section. SYNC byte and ACK byte, respectively. Events such as device wake-up and interrupt generate transitions on the control channel that should be ignored by the FC.
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MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer UART-TO-I2C CONVERSION OF WRITE PACKET (I2CMETHOD = 0) FC SERIALIZER/DESERIALIZER 11 SYNC FRAME SERIALIZER/DESERIALIZER 11 DEVICE ID + WR 11 REGISTER ADDRESS 11 NUMBER OF BYTES 11 DATA 0 11 DATA N 11 ACK FRAME PERIPHERAL 1 S 7 DEV ID 1 1 W A 8 REG ADDR 8 DATA 0 1 A 1 A 8 DATA N 1 1 A P UART-TO-I2C CONVERSION OF READ PACKET (I2CMETHOD = 0) FC SERIALIZER/DESERIALIZER 11 SYNC FRAME SERIALIZER/DESERIALIZER 11 DEVICE
PAGE 34
MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer UART-TO-I2C CONVERSION OF WRITE PACKET (I2CMETHOD = 1) FC 11 SYNC FRAME SERIALIZER/DESERIALIZER 11 DEVICE ID + WR SERIALIZER/DESERIALIZER FC 11 REGISTER ADDRESS PERIPHERAL 1 7 S DEV ID 11 NUMBER OF BYTES 11 DATA N 1 1 W A 8 DATA 0 UART-TO-I2C CONVERSION OF READ PACKET (I2CMETHOD = 1) SERIALIZER/DESERIALIZER 11 11 11 SYNC FRAME DEVICE ID + RD REGISTER ADDRESS SERIALIZER/DESERIALIZER 11 DATA 0 11 NUMBER OF BYTES 11 ACK F
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MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer Table 4. Serializer CML Driver Strength (Default Level, CMLLVL = 11) SINGLE-ENDED VOLTAGE SWING PREEMPHASIS LEVEL (dB)* PREEMPHASIS SETTING (0x05, D[3:0]) ICML (mA) IPRE (mA) MAX (mV) MIN (mV) -6.0 0100 12 4 400 200 -4.1 0011 13 3 400 250 -2.5 0010 14 2 400 300 -1.2 0001 15 1 400 350 0 0000 16 0 400 400 1.1 1000 16 1 425 375 2.2 1001 16 2 450 350 3.3 1010 16 3 475 325 4.
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MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer Spread Spectrum To reduce the EMI generated by the transitions on the serial link and parallel outputs, both the serializer and deserializer support spread spectrum. Turning on spread spectrum on the deserializer spreads the parallel video outputs. Turning on spread spectrum on the serializer spreads the serial link, along with the deserializer parallel outputs. Do not enable spread for both the serializer and deserializer.
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MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer Manual Programming of the Spread-Spectrum Divider Sleep Mode The serializer/deserializer include a low-power sleep mode to reduce power consumption on the device not attached to the FC (the deserializer in LCD applications and the serializer in camera applications). Set the corresponding remote IC’s SLEEP bit to 1 to initiate sleep mode. The serializer sleeps immediately after setting its SLEEP = 1.
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MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer outputs of the device remain high impedance. Entering power-down mode resets the internal registers of the device. In addition, upon exiting power-down mode, the serializer/deserializer relatch the state of external pins SSEN, DRS, AUTOS, and EQS. Configuration Link Mode The GMSL includes a low-speed configuration link to allow control-data connection between the two devices in the absence of a valid clock input.
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MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer Case 3: Remote Side Autostart Mode After power-up or when PWDN transitions from low to high, the remote device (deserializer) starts up and tries to lock to an incoming serial signal with sufficient power. The host side (serializer) is in standby mode and does not try to establish a link.
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MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer SLEEP = 1, VIDEO LINK OR CONFIG LINK NOT LOCKED AFTER 8ms MS PIN SETTING SLEEP BIT POWER-UP VALUE LOW HIGH 0 1 SLEEP WAKE-UP SIGNAL POWER-ON IDLE SERIAL LINK ACTIVITY STOPS OR 8ms ELAPSES AFTER FC SETS SLEEP = 1 SEND INT TO PWDN = HIGH, POWER-ON INT CHANGES FROM LOW TO HIGH OR HIGH TO LOW SIGNAL DETECTED CONFIG LINK UNLOCKED SERIAL PORT LOCKING CONFIG LINK OPERATING PROGRAM REGISTERS CONFIG LINK LOCKED VIDEO LINK LO
PAGE 41
MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer AUTOS PIN SETTING LOW HIGH POWER-UP VALUE SEREN SLEEP 1 0 0 1 SLEEP CLINKEN = 0 OR SEREN = 1 CLINKEN = 0 OR SEREN = 1 SLEEP = 1 FOR > 8ms SLEEP = 0, WAKE-UP REVERSE LINK POWER-ON IDLE SEREN = 0 CONFIG LINK STARTED CLINKEN = 1 WAKE-UP SIGNAL PWDN = HIGH, POWER-ON, AUTOS = HIGH SLEEP = 1 ALL STATES PWDN = LOW OR POWER-OFF POWER-DOWN OR POWER-OFF SLEEP = 0, SLEEP = 1 SEREN = 1, PCLKIN RUNNING PWDN = HIGH, POWER-ON AU
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MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer then reads the deserializer KSV (BKSV) and writes it to the serializer. The FC begins checking BKSV against the revocation list. Using the cipher, the serializer and deserializer calculate a 16-bit response value, R0 and R0’, respectively. The GMSL amendment for HDCP reduces the 100ms minimum wait time allowed for the receiver to generate R0’ (specified in HDCP rev 1.3) to 128 pixel clock cycles in the GMSL amendment.
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MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer Force Video/Force Audio Data HDCP Authentication Procedures authentication procedure. The serializer and deserializer generate HDCP authentication response values for the verification of authentication. Use the following procedures to authenticate the HDCP-GMSL encryption. Refer to the HDCP 1.3 Amendment for GMSL for details. The FC must perform link integrity checks while encryption is enabled.
PAGE 44
MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer Table 13. Startup, HDCP Authentication, and Normal Operation (Deserializer is not a Repeater)—First Part of the HDCP Authentication Protocol (continued) NO. µC SERIALIZER DESERIALIZER 8 Reads the BKSV and REPEATER bit from the deserializer and writes to the serializer. Generates R0, triggered by the FC’s write of BKSV. — 9 Reads the INVALID_BKSV bit of the serializer and continues with authentication if it is 0.
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MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer Table 14. Link Integrity Check (Normal)—Performed Every 128 Frames After Encryption is Enabled (continued) NO. µC 8 If RI does not match RI’, link integrity check fails. After the detection of failure of link integrity check, the FC ensures that A/V data not requiring protection (low-value content) is available at the serializer inputs (such as blue or informative screen).
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MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer Example Repeater Network—Two µCs The following example has one repeater and two FCs (Figure 34). Table 16 summarizes the authentication operation. BD-DRIVE TX_B1 REPEATER DISPLAY 1 RX_R1 TX_R1 RX_D1 VIDEO ROUTING µC_B MEMORY WITH SRM RX_R2 µC_R DISPLAY 2 RX_D2 TX_R2 VIDEO CONNECTION CONTROL CONNECTION 1 (µC_B IN BD-DRIVE IS MASTER) CONTROL CONNECTION 2 (µC_R IN REPEATER IS MASTER) Figure 34.
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MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer Table 16. HDCP Authenticaion and Normal Operation (One Repeater, Two µCs)—First and Second Parts of the HDCP Authentication Protocol (continued) NO. µC_B 3 Makes sure that the A/V data not requiring protection (low-value content) is available at the TX_B1 inputs (such as blue or informative screen). Alternatively, the FORCE_ VIDEO and FORCE_AUDIO bits of TX_B1 can be used to mask the A/V data input of TX_B1.
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MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer Table 16. HDCP Authenticaion and Normal Operation (One Repeater, Two µCs)—First and Second Parts of the HDCP Authentication Protocol (continued) NO. µC_B 9 Waits for the VSYNC falling edge and then enables encryption on the (TX_B1, RX_R1) link. Full authentication is not yet complete, so it ensures that A/V content that needs protection is not transmitted.
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MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer Table 16. HDCP Authenticaion and Normal Operation (One Repeater, Two µCs)—First and Second Parts of the HDCP Authentication Protocol (continued) NO. µC_B 14 Reads the KSV list and BINFO from RX_R1 and writes them to TX_B1. If any of the MAX_DEVS_EXCEEDED or MAX_CASCADE_EXCEEDED bits is 1, then authentication fails. Note: BINFO must be written after the KSV list.
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MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer Applications Information Error Checking The deserializer checks the serial link for errors and stores the number of detected decoding errors in the 8-bit register DECERR (0x0D). If a large number of 8b/10b decoding or parity errors are detected within a short duration (error rate R 1/4), the deserializer loses lock and stops the error counter. The deserializer then attempts to relock to the serial data.
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MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer Jitter-Filtering PLL In some applications, the parallel bus input clock to the serializer (PCLKIN) includes noise, which reduces link reliability. The serializer has a narrowband jitter-filtering PLL to attenuate frequency components outside the PLL’s bandwidth (< 100kHz typ). Enable the jitter-filtering PLL by setting DISFPLL = 0 (0x05, D6).
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MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer required external resistor connections. LFLT = low when a line fault is detected and LFLT goes high when the line returns to normal. The line-fault type is stored in 0x08, D[3:0] of the serializer. Filter LFLT with the FC to reduce the detector’s susceptibility to brief ground shifts. The fault detector threshold voltages are referenced to the serializer ground. Additional passive components set the DC level of the cable (Figure 3).
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MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer AC-Coupling matched differential impedance to minimize impedance discontinuities. Twisted-pair and shielded twisted-pair cables tend to generate less EMI due to magnetic-field canceling effects. Balanced cables pick up noise as common-mode rejected by the CML receiver. Table 19 lists the suggested cables and connectors used in the GMSL link.
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MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer RD 330I HIGHVOLTAGE DC SOURCE CHARGE-CURRENTLIMIT RESISTOR CS 150pF RD 2kI DISCHARGE RESISTANCE HIGHVOLTAGE DC SOURCE DEVICE UNDER TEST STORAGE CAPACITOR Figure 36. IEC 61000-4-2 Contact Discharge ESD Test Circuit CHARGE-CURRENTLIMIT RESISTOR CS 330pF DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST Figure 37. ISO 10605 Contact Discharge ESD Test Circuit Table 20.
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MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer Table 20. Serializer GMSL Core Register Table (continued) REGISTER ADDRESS BITS D[7:6] NAME D7 SDIV CLINKEN D5 PRBSEN 0x04 D[3:2] Calibrate spread-modulation rate only once after locking. 01 Calibrate spread-modulation rate every 2ms after locking. 10 Calibrate spread-modulation rate every 16ms after locking. 11 Calibrate spread-modulation rate every 256ms after locking. 000000 Autocalibrate sawtooth divider.
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MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer Table 20. Serializer GMSL Core Register Table (continued) REGISTER ADDRESS BITS NAME D7 I2CMETHOD D6 DISFPLL D[5:4] CMLLVL 0x05 D[3:0] PREEMP FUNCTION 0 I2C conversion sends the register address. 1 Disable sending of I2C register address (command-byte-only mode). 0 Filter PLL active. 1 Filter PLL disabled. 00 Do not use. 01 200mV CML signal level. 10 300mV CML signal level. 11 400mV CML signal level.
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MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer Table 20. Serializer GMSL Core Register Table (continued) REGISTER ADDRESS 0x0D 0x1E 0x1F BITS NAME VALUE D7 SETINT D6 INVVSYNC D5 INVHSYNC D[4:0] — 00000 D[7:0] ID 00000101 D[7:5] — 000 D4 CAPS D[3:0] REVISION FUNCTION 0 Set INT low when SETINT transitions from 1 to 0. 1 Set INT high when SETINT transitions from 0 to 1. 0 Serializer does not invert DIN19/VS. 1 Serializer inverts DIN19/VS.
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MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer Table 21. Deserializer GMSL Core Register Table (continued) REGISTER ADDRESS BITS D[7:6] NAME VALUE 00 Calibrate spread-modulation rate only once after locking. 01 Calibrate spread-modulation rate every 2ms after locking. 10 Calibrate spread-modulation rate every 16ms after locking. 11 Calibrate spread-modulation rate every 256ms after locking. 0 Reserved.
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MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer Table 21. Deserializer GMSL Core Register Table (continued) REGISTER ADDRESS BITS D7 D[6:5] D4 NAME I2CMETHOD HPFTUNE PDHF 0x05 D[3:0] 0x06 Maxim Integrated EQTUNE D7 DISSTAG D6 AUTORST D5 DISINT D4 INT D3 GPIO1OUT D2 GPIO1 D1 GPIO0OUT D0 GPIO0 VALUE FUNCTION 0 I2C conversion sends the register address. 1 Disable sending of I2C register address (command-byte-only mode). 00 7.
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MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer Table 21. Deserializer GMSL Core Register Table (continued) REGISTER ADDRESS BITS NAME VALUE 0x07 D[7:0] — 01010100 Reserved. 01010100 D[7:2] — 001100 Reserved. 001100 FUNCTION 0 VSYNC glitch filter active. 1 VSYNC glitch filter disabled. 0 HSYNC glitch filter active. 1 HSYNC glitch filter disabled. DEFAULT VALUE D1 DISVSFILT D0 DISHSFILT 0x09 D[7:0] — 11001000 Reserved.
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MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer Table 22.
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MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer Table 22.
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MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer Table 22. Serializer HDCP Register Table (continued) REGISTER ADDRESS 0xB0 to 0xB3 SIZE (Bytes) 4 NAME V.H4, V’.
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MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer Table 23.
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MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer Table 23.
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MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer Typical Application Circuit PCLK RGB HS VS DE GPU PCLKIN DIN[17:0] DIN18/HS DIN19/VS DIN20 PCLK RGB HSYNC VSYNC DE PCLKOUT DOUT[17:0] DOUT18/HS DOUT19/VS DOUT20 CDS 45.3kI 45.3kI 4.99kI 4.99kI CDS AUTOS LMN1 LMN0 ECU MAX9263 UART TX RX LFLT INT MS RX/SDA TX/SCL MAX9264 DISPLAY OUT+ IN+ OUT- IN49.9kI LFLT INT MS TO PERIPHERALS INT RX/SDA TX/SCL 49.
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MAX9263/MAX9264 HDCP Gigabit Multimedia Serial Link Serializer/Deserializer Revision History REVISION NUMBER REVISION DATE 0 12/10 Initial release — 1 3/11 Updated the MAX9263 SCK and WS pin descriptions 14 DESCRIPTION Updated General Description and Features sections, Figure 6, and Typical 2 9/14 Application Circuit, clarified function, removed Tables 1 and 2, and renumbered subsequent tables PAGES CHANGED 1, 5, 14–18, 22, 24, 29–31, 33–38, 40, 43–49, 52–66 Maxim Integrated cannot assume re