User`s manual

5.2 Parallel Bus
5.2.1 Timing Diagram
Address
Data
Data
Address
Phase
Data
Phase
t1 t2
t3 t4
CLKOUTA
A12-A0
/CS
/RD
D7-D0
(Read)
/WR
D7-D0
(Write)
Address
Phase
Data
Phase
t1 t2
t3 t4
CLKOUTA
ARDY (Normally
Not-Ready System)
ARDY (Normally
Ready System)
Case 2
Case 4
Case 1
Case 3
t4
twt3t2
t4twtw
tw
t4tw
twt3
I/O Expansion Bus for 7188X/7188E User’s Manual, Jun/2004 v1.4, 7PH-000-14---25