Data Sheet
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Espressif Systems
ESP8266 Datasheet
• WMM power save U-APSD;"
• Multiple queue management to fully utilize traffic prioritization defined by 802.11e standard;"
• UMA compliant and certified;"
• 802.1h/RFC1042 frame encapsulation;"
• Scattered DMA for optimal CPU off load on Zero Copy data transfer operations;"
• Antenna diversity and selection (software managed hardware);"
• Clock/power gating combined with 802.11-compliant power management dynamically adapted
to current connection condition providing minimal power consumption;"
• Adaptive rate fallback algorithm sets the optimum transmission rate and Tx power based on
actual SNR and packet loss information;"
• Automatic retransmission and response on MAC to avoid packet discarding on slow host
environment;"
• Seamless roaming support;"
• Configurable packet traffic arbitration (PTA) with dedicated slave processor based design
provides flexible and exact timing Bluetooth co-existence support for a wide range of Bluetooth
Chip vendors;"
• Dual and single antenna Bluetooth co-existence support with optional simultaneous receive
(WiFi/Bluetooth) capability."
5. Power Management
The chip can be put into the following states:
• OFF: CHIP_PD pin is low. The RTC is disabled. All registers are cleared.
• DEEP_SLEEP: Only RTC is powered on – the rest of the chip is powered off. Recovery memory
of RTC can keep basic WiFi connecting information.
• SLEEP: Only the RTC is operating. The crystal oscillator is disabled. Any wakeup events (MAC,
host, RTC timer, external interrupts) will put the chip into the WAKEUP state.
• WAKEUP: In this state, the system goes from the sleep states to the PWR state. The crystal
oscillator and PLLs are enabled.
• ON: the high speed clock is operational and sent to each block enabled by the clock control
register. Lower level clock gating is implemented at the block level, including the CPU, which
can be gated off using the WAITI instruction, while the system is on.
Espressif Systems / August 1, 2015
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