SoftStore nvSRAM Specification Sheet
Table Of Contents
- Features
- Functional Description
- Logic Block Diagram
- Pin Configurations
- Device Operation
- SRAM Read
- SRAM Write
- Software STORE
- Software RECALL
- Hardware RECALL (Power Up)
- Hardware Protect
- Noise Considerations
- Low Average Active Power
- Best Practices
- Maximum Ratings
- Operating Range
- DC Electrical Characteristics
- Data Retention and Endurance
- Capacitance
- Thermal Resistance
- AC Test Conditions
- Switching Waveforms
- Switching Waveforms
- STORE INHIBIT or Power Up RECALL
- Switching Waveforms
- Software Controlled STORE/RECALL Cycle
- Switching Waveforms
- Part Numbering Nomenclature
- Ordering Information
- Document History Page
- Sales, Solutions and Legal Information
STK11C88
Document Number: 001-50591 Rev. ** Page 11 of 15
Software Controlled STORE/RECALL Cycle
The software controlled STORE/RECALL cycle follows.
[11, 12]
Parameter Alt Description
25 ns 45 ns
Unit
Min Max Min Max
t
RC
t
AVAV
STORE/RECALL Initiation Cycle Time 25 45 ns
t
SA
[11]
t
AVEL
Address Setup Time 0 0 ns
t
CW
[11]
t
ELEH
Clock Pulse Width 20 30 ns
t
HACE
[11]
t
ELAX
Address Hold Time 20 20 ns
t
RECALL
[11]
RECALL Duration 20 20 μs
Switching Waveforms
Figure 10. CE Controlled Software STORE/RECALL Cycle
[12]
t
RC
t
RC
t
SA
t
SCE
t
HACE
t
STORE
/ t
RECALL
DATA VALID
DATA VALID
6#SSERDDA1#SSERDDA
HIGH IMPEDANCE
ADDRESS
CE
OE
DQ (DATA)
Notes
11. The software sequence is clocked on the falling edge of CE
without involving OE (double clocking abort the sequence).
12. The six consecutive addresses must be read in the order listed in the Mode Selection table. WE
must be HIGH during all six consecutive cycles.
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